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This commit is contained in:
Miodrag Milanovic 2026-03-26 08:24:06 +01:00
parent 604df0d7fb
commit a8485a2adf
3 changed files with 3 additions and 3 deletions

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@ -11,7 +11,7 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 6 t:LUTFF
select -assert-max 5 t:LUT2
select -assert-max 4 t:LUT3

View file

@ -5,4 +5,4 @@ sys.path.append("..")
import gen_tests_makefile
gen_tests_makefile.generate(["--yosys-scripts"])
gen_tests_makefile.generate(["--yosys-scripts"])

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@ -55,4 +55,4 @@ gen_tests_makefile.generate_autotest("*.v", "",
if grep -q expect-no-rd-clk $@; then \\
grep -Fq "connect \\\\RD_CLK 1'x" $(@:.v=).dmp || { echo " ERROR: Expected no read clock."; exit 1; }; \\
fi; \\
fi""")
fi""")