mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-26 22:35:47 +00:00
Cleanup
This commit is contained in:
Miodrag Milanovic
parent
5ef1d9fa1d
commit
604df0d7fb
8 changed files with 75 additions and 76 deletions
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@ -11,6 +11,9 @@ import os
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def base(fn):
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return os.path.splitext(fn)[0]
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def cmd(lines):
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return " \\\n".join(lines)
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# NB: *.aag and *.aig must contain a symbol table naming the primary
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# inputs and outputs, otherwise ABC and Yosys will name them
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# arbitrarily (and inconsistently with each other).
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@ -24,7 +27,7 @@ def create_tests():
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for aag in aags:
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b = base(aag)
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cmd = [
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gen_tests_makefile.generate_target(aag, cmd([
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f"$(ABC) -q \"read -c {b}.aig; write {b}_ref.v\";",
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"$(YOSYS) -qp \"",
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f"read_verilog {b}_ref.v;",
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@ -38,20 +41,18 @@ def create_tests():
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"miter -equiv -flatten -make_assert -make_outputs gold gate miter;",
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"sat -verify -prove-asserts -show-ports -seq 16 miter;",
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f"\" -l {aag}.log"
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]
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gen_tests_makefile.generate_cmd_test(aag, cmd)
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]))
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# ---- Yosys script tests ----
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for ys in yss:
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gen_tests_makefile.generate_ys_test(ys)
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cmd = [ "rm -rf gate; mkdir gate;",
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"$(YOSYS) --no-version -p \"test_cell -aigmap -w gate/ -n 1 -s 1 all\";",
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"set -o pipefail; diff --brief gold gate | tee aigmap.err;",
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"rm -f aigmap.err" ]
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gen_tests_makefile.generate_cmd_test("aigmap", cmd)
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gen_tests_makefile.generate_target("aigmap", cmd([
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"rm -rf gate; mkdir gate;",
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"$(YOSYS) --no-version -p \"test_cell -aigmap -w gate/ -n 1 -s 1 all\";",
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"set -o pipefail; diff --brief gold gate | tee aigmap.err;",
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"rm -f aigmap.err"
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]))
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extra = [ f"ABC ?= {gen_tests_makefile.yosys_basedir}/yosys-abc", "SHELL := /bin/bash" ]
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@ -7,13 +7,13 @@ import gen_tests_makefile
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def run_subtest(name):
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gen_tests_makefile.generate_cmd_test(f"cxxrtl_{name}", [
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f"$${{CXX:-g++}} -std=c++11 -O2 -o cxxrtl-test-{name} -I../../backends/cxxrtl/runtime test_{name}.cc -lstdc++;",
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f"$${{CXX:-g++}} -std=c++11 -O2 -o cxxrtl-test-{name} -I../../backends/cxxrtl/runtime test_{name}.cc -lstdc++",
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f"./cxxrtl-test-{name}",
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])
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def compile_only():
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gen_tests_makefile.generate_cmd_test("cxxrtl_unconnected_output", [
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'$(YOSYS) -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc";',
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'$(YOSYS) -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"',
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f'$${{CXX:-g++}} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc',
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])
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@ -5,16 +5,13 @@ sys.path.append("..")
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import gen_tests_makefile
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def cmd(lines):
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return " && \\\n".join(lines)
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def initial_display():
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gen_tests_makefile.generate_target("initial_display", cmd([
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gen_tests_makefile.generate_cmd_test("initial_display", [
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f"$(YOSYS) -p \"read_verilog initial_display.v\" | awk '/<<<BEGIN>>>/,/<<<END>>>/ {{print $$0}}' >yosys-initial_display.log 2>&1",
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"iverilog -o iverilog-initial_display initial_display.v",
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"./iverilog-initial_display >iverilog-initial_display.log",
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"diff yosys-initial_display.log iverilog-initial_display.log",
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]))
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])
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def always_display():
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@ -28,11 +25,11 @@ def always_display():
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]
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for name, defs in cases:
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gen_tests_makefile.generate_target(f"always_display_{name}", cmd([
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gen_tests_makefile.generate_cmd_test(f"always_display_{name}", [
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f"$(YOSYS) -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v",
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f"$(YOSYS) -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v",
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f"diff yosys-always_display-{name}-1.v yosys-always_display-{name}-2.v",
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]))
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])
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def roundtrip():
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@ -48,7 +45,7 @@ def roundtrip():
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]
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for name, defs in cases:
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gen_tests_makefile.generate_target(f"roundtrip_{name}", cmd([
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gen_tests_makefile.generate_cmd_test(f"roundtrip_{name}", [
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f"$(YOSYS) -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v",
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f"$(YOSYS) -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v",
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f"diff yosys-roundtrip-{name}-1.v yosys-roundtrip-{name}-2.v",
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@ -64,14 +61,14 @@ def roundtrip():
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f"diff iverilog-roundtrip-{name}.log iverilog-roundtrip-{name}-1.log",
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f"diff iverilog-roundtrip-{name}-1.log iverilog-roundtrip-{name}-2.log",
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]))
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])
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def cxxrtl():
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cases = ["always_full", "always_comb"]
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for name in cases:
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gen_tests_makefile.generate_target(f"cxxrtl_{name}", cmd([
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gen_tests_makefile.generate_cmd_test(f"cxxrtl_{name}", [
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f"$(YOSYS) -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\"",
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f"$${{CXX:-g++}} -std=c++11 -o yosys-{name} -I../../backends/cxxrtl/runtime {name}_tb.cc -lstdc++",
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f"./yosys-{name} 2>yosys-{name}.log",
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@ -80,19 +77,19 @@ def cxxrtl():
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f"./iverilog-{name} | grep -v \"$finish called\" >iverilog-{name}.log",
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f"diff iverilog-{name}.log yosys-{name}.log",
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]))
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])
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def extra():
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gen_tests_makefile.generate_target("always_full_equiv", cmd([
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gen_tests_makefile.generate_cmd_test("always_full_equiv", [
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"$(YOSYS) -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v",
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"iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v",
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"./iverilog-always_full-1 > tmp.log",
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"grep -v '\\$finish called' tmp.log > iverilog-always_full-1.log",
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"diff iverilog-always_full.log iverilog-always_full-1.log",
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]), deps=["cxxrtl_always_full"])
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], deps=["cxxrtl_always_full"])
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gen_tests_makefile.generate_target("display_lm", cmd([
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gen_tests_makefile.generate_cmd_test("display_lm", [
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"$(YOSYS) -p \"read_verilog display_lm.v\" >yosys-display_lm.log 2>&1",
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"$(YOSYS) -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\"",
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f"$${{CXX:-g++}} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++",
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@ -101,7 +98,7 @@ def extra():
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"grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm.log\"",
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"grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"",
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"grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"",
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]))
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])
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def main():
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@ -56,11 +56,11 @@ def unpack_cmd(cmd):
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if isinstance(cmd, str):
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return cmd
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if isinstance(cmd, (list, tuple)):
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return " \\\n".join(cmd)
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return " && \\\n".join(cmd)
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raise TypeError("cmd must be a string or a list/tuple of strings")
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def generate_cmd_test(test_name, cmd, yosys_args=""):
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generate_target(test_name, unpack_cmd(cmd))
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def generate_cmd_test(test_name, cmd, yosys_args="", deps = None):
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generate_target(test_name, unpack_cmd(cmd), deps)
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def generate_tests(argv, cmds):
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parser = argparse.ArgumentParser(add_help=False)
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@ -12,13 +12,13 @@ def lib_tests():
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base = os.path.splitext(lib)[0]
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gen_tests_makefile.generate_cmd_test(lib, [
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f'$(YOSYS) -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty {lib}" -ql {base}.log;',
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f'$(YOSYS) -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty {lib}" -ql {base}.log',
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f'../../yosys-filterlib - {lib} > {lib}.filtered;',
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f'../../yosys-filterlib -verilogsim {lib} > {lib}.verilogsim;',
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f'$(YOSYS_FILTERLIB) - {lib} > {lib}.filtered',
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f'$(YOSYS_FILTERLIB) -verilogsim {lib} > {lib}.verilogsim',
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f'diff {lib}.filtered {lib}.filtered.ok;',
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f'diff {lib}.verilogsim {lib}.verilogsim.ok;',
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f'diff {lib}.filtered {lib}.filtered.ok',
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f'diff {lib}.verilogsim {lib}.verilogsim.ok',
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f'if [ -e {base}.log.ok ]; then '
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f'$(YOSYS) -p "dfflibmap -info -liberty {lib}" -TqqQl {base}.log; '
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@ -36,7 +36,8 @@ def main():
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lib_tests()
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ys_tests()
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gen_tests_makefile.generate_custom(callback)
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gen_tests_makefile.generate_custom(callback,
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[f"YOSYS_FILTERLIB ?= {gen_tests_makefile.yosys_basedir}/yosys-filterlib"])
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if __name__ == "__main__":
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@ -9,59 +9,59 @@ def create_tests():
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setup = "mkdir -p temp && cp content1.dat temp/content2.dat"
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gen_tests_makefile.generate_cmd_test("parent_content1", [
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f"{setup};",
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'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;',
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'chparam -set MEMFILE \\"content1.dat\\" memory"',
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f"{setup}",
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'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v; '
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'chparam -set MEMFILE \\"content1.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("parent_content2_temp", [
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f"{setup};",
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'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;',
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"',
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f"{setup}",
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'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v; '
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("parent_content2_full", [
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f"{setup};",
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'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;',
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'chparam -set MEMFILE \\"memfile/temp/content2.dat\\" memory"',
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f"{setup}",
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'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v; '
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'chparam -set MEMFILE \\"memfile/temp/content2.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("same_content1", [
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f"{setup};",
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'$(YOSYS) -qp "read_verilog -defer memory.v;',
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'chparam -set MEMFILE \\"content1.dat\\" memory"',
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f"{setup}",
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'$(YOSYS) -qp "read_verilog -defer memory.v; '
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'chparam -set MEMFILE \\"content1.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("same_content2", [
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f"{setup};",
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'$(YOSYS) -qp "read_verilog -defer memory.v;',
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"',
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f"{setup}",
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'$(YOSYS) -qp "read_verilog -defer memory.v; '
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("child_content1", [
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f"{setup};",
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'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;',
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'chparam -set MEMFILE \\"content1.dat\\" memory"',
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f"{setup}",
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'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
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'chparam -set MEMFILE \\"content1.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("child_content2_temp", [
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f"{setup};",
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'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;',
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"',
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f"{setup}",
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'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("child_content2_direct", [
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f"{setup};",
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'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;',
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"',
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f"{setup}",
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'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
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'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
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])
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gen_tests_makefile.generate_cmd_test("fail_empty_filename",
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'! $(YOSYS) -qp "read_verilog memory.v"')
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gen_tests_makefile.generate_cmd_test("fail_missing_file", [
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'! $(YOSYS) -qp "read_verilog -defer memory.v;',
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'chparam -set MEMFILE \\"content3.dat\\" memory"',
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'! $(YOSYS) -qp "read_verilog -defer memory.v; '
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'chparam -set MEMFILE \\"content3.dat\\" memory"'
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])
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extra = ["YOSYS_ABS := $(abspath $(YOSYS))"]
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@ -100,8 +100,8 @@ for idx in range(args.count):
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def create_tests():
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for idx in range(args.count):
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cmd = [
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f"$(YOSYS) -qq uut_{idx:05d}.ys &&",
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f"iverilog -o uut_{idx:05d}_tb uut_{idx:05d}_tb.v uut_{idx:05d}.v uut_{idx:05d}_syn.v &&",
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f"$(YOSYS) -qq uut_{idx:05d}.ys",
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f"iverilog -o uut_{idx:05d}_tb uut_{idx:05d}_tb.v uut_{idx:05d}.v uut_{idx:05d}_syn.v",
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f"./uut_{idx:05d}_tb"
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# f"./uut_{idx:05d}_tb | tee uut_{idx:05d}.err;",
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# f"if test -s uut_{idx:05d}.err; then",
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@ -15,18 +15,18 @@ runone_tests = [
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def run_one():
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for testname in runone_tests:
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cmd_lines = [
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f'$(YOSYS) -p "read_verilog -sv {testname}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;',
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f'$(YOSYS) -p "read_verilog -sv {testname}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_ref_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;',
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f'rm -f a.out reference_result.txt dut_result.txt;',
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f'iverilog -g2012 {testname}_syn.v;',
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f'iverilog -g2012 {testname}_ref_syn.v;',
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f'iverilog -g2012 {testname}_tb.v {testname}_ref_syn.v;',
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f'./a.out;',
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f'mv output.txt reference_result.txt;',
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f'iverilog -g2012 {testname}_tb_wrapper.v {testname}_syn.v;' if testname=="svinterface_at_top" else
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f'iverilog -g2012 {testname}_tb.v {testname}_syn.v;',
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f'./a.out;',
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f'mv output.txt dut_result.txt;',
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f'$(YOSYS) -p "read_verilog -sv {testname}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr',
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f'$(YOSYS) -p "read_verilog -sv {testname}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_ref_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr',
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f'rm -f a.out reference_result.txt dut_result.txt',
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f'iverilog -g2012 {testname}_syn.v',
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f'iverilog -g2012 {testname}_ref_syn.v',
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f'iverilog -g2012 {testname}_tb.v {testname}_ref_syn.v',
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f'./a.out',
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f'mv output.txt reference_result.txt',
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f'iverilog -g2012 {testname}_tb_wrapper.v {testname}_syn.v' if testname=="svinterface_at_top" else
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f'iverilog -g2012 {testname}_tb.v {testname}_syn.v',
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f'./a.out',
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f'mv output.txt dut_result.txt',
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f'diff reference_result.txt dut_result.txt > {testname}.diff',
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]
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gen_tests_makefile.generate_cmd_test(testname, cmd_lines)
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