diff --git a/tests/arch/fabulous/fsm.ys b/tests/arch/fabulous/fsm.ys
index 15fd19247..5f7ae28dd 100644
--- a/tests/arch/fabulous/fsm.ys
+++ b/tests/arch/fabulous/fsm.ys
@@ -11,7 +11,7 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
-stat
+
 select -assert-count 6 t:LUTFF
 select -assert-max 5 t:LUT2
 select -assert-max 4 t:LUT3
diff --git a/tests/blif/generate_mk.py b/tests/blif/generate_mk.py
index 96aa6be79..6a921d5a0 100644
--- a/tests/blif/generate_mk.py
+++ b/tests/blif/generate_mk.py
@@ -5,4 +5,4 @@ sys.path.append("..")
 
 import gen_tests_makefile
 
-gen_tests_makefile.generate(["--yosys-scripts"])
\ No newline at end of file
+gen_tests_makefile.generate(["--yosys-scripts"])
diff --git a/tests/memories/generate_mk.py b/tests/memories/generate_mk.py
index 0df27bc5e..cfb29acb9 100644
--- a/tests/memories/generate_mk.py
+++ b/tests/memories/generate_mk.py
@@ -55,4 +55,4 @@ gen_tests_makefile.generate_autotest("*.v", "",
 	if grep -q expect-no-rd-clk $@; then \\
 		grep -Fq "connect \\\\RD_CLK 1'x" $(@:.v=).dmp || { echo " ERROR: Expected no read clock."; exit 1; }; \\
 	fi; \\
-fi""")
\ No newline at end of file
+fi""")