diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index de077415f..e36e006ac 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -65,6 +65,10 @@ struct CheckPass : public Pass {
 		log("        $_DLATCH_*/$_DLATCHSR_* mappings) remaining in the design. Use this\n");
 		log("        before techmapping in flows that must not emit latches.\n");
 		log("\n");
+		log("    -latchonly\n");
+		log("        check only for latch cells (as listed under -nolatches), skipping all\n");
+		log("        other checks.\n");
+		log("\n");
 		log("    -allow-tbuf\n");
 		log("        modify the -mapped behavior to still allow $_TBUF_ cells\n");
 		log("\n");
@@ -85,6 +89,7 @@ struct CheckPass : public Pass {
 		bool initdrv = false;
 		bool mapped = false;
 		bool nolatches = false;
+		bool latchonly = false;
 		bool allow_tbuf = false;
 		bool assert_mode = false;
 		bool force_detailed_loop_check = false;
@@ -108,6 +113,10 @@ struct CheckPass : public Pass {
 				nolatches = true;
 				continue;
 			}
+			if (args[argidx] == "-latchonly") {
+				latchonly = true;
+				continue;
+			}
 			if (args[argidx] == "-allow-tbuf") {
 				allow_tbuf = true;
 				continue;
@@ -124,8 +133,6 @@ struct CheckPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		bool latchonly = design->scratchpad_get_bool("check.latchonly", false);
-
 		log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
 
 		for (auto module : design->selected_whole_modules_warn())
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 60d72895c..8faa49fcb 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -204,12 +204,9 @@ struct SynthEfinixPass : public ScriptPass
 		{
 			run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
 			if (help_mode)
-				run("check -assert", "(only if -latches error, the default)");
-			else if (latches == "error") {
-				active_design->scratchpad_set_bool("check.latchonly", true);
-				run("check -assert");
-				active_design->scratchpad_unset("check.latchonly");
-			}
+				run("check -latchonly -assert", "(only if -latches error, the default)");
+			else if (latches == "error")
+				run("check -latchonly -assert");
 			run("techmap -D NO_LUT -map +/efinix/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
index 57d4286f4..ecf59a376 100644
--- a/techlibs/fabulous/synth_fabulous.cc
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -373,12 +373,9 @@ struct SynthPass : public ScriptPass
 				run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
 			}
 			if (help_mode)
-				run("check -assert", "(only if -latches error, the default)");
-			else if (latches == "error") {
-				active_design->scratchpad_set_bool("check.latchonly", true);
-				run("check -assert");
-				active_design->scratchpad_unset("check.latchonly");
-			}
+				run("check -latchonly -assert", "(only if -latches error, the default)");
+			else if (latches == "error")
+				run("check -latchonly -assert");
 			run("techmap -map +/fabulous/latches_map.v");
 			run("techmap -map +/fabulous/ff_map.v");
 			if (help_mode) {
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 5a27d5de8..fa5b7c0db 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -420,12 +420,9 @@ struct SynthIce40Pass : public ScriptPass
 				run("ice40_opt", "(only if -abc2)");
 			}
 			if (help_mode)
-				run("check -assert", "(only if -latches error, the default)");
-			else if (latches == "error") {
-				active_design->scratchpad_set_bool("check.latchonly", true);
-				run("check -assert");
-				active_design->scratchpad_unset("check.latchonly");
-			}
+				run("check -latchonly -assert", "(only if -latches error, the default)");
+			else if (latches == "error")
+				run("check -latchonly -assert");
 			run("techmap -map +/ice40/latches_map.v");
 			if (noabc || flowmap || help_mode) {
 				run("simplemap", "                               (if -noabc or -flowmap)");
diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc
index ec3520616..cf2d19a1a 100644
--- a/techlibs/lattice/synth_lattice.cc
+++ b/techlibs/lattice/synth_lattice.cc
@@ -548,12 +548,9 @@ struct SynthLatticePass : public ScriptPass
 				run("abc", "      (only if -abc2)");
 			if (!asyncprld || help_mode) {
 				if (help_mode)
-					run("check -assert", "(skip if -asyncprld; only if -latches error, the default)");
-				else if (latches == "error") {
-					active_design->scratchpad_set_bool("check.latchonly", true);
-					run("check -assert");
-					active_design->scratchpad_unset("check.latchonly");
-				}
+					run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)");
+				else if (latches == "error")
+					run("check -latchonly -assert");
 				run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
 			}
 
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 9aeb6e2d4..664c9313a 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -340,12 +340,9 @@ struct SynthNanoXplorePass : public ScriptPass
 			run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
 			run("opt_merge");
 			if (help_mode)
-				run("check -assert", "(only if -latches error, the default)");
-			else if (latches == "error") {
-				active_design->scratchpad_set_bool("check.latchonly", true);
-				run("check -assert");
-				active_design->scratchpad_unset("check.latchonly");
-			}
+				run("check -latchonly -assert", "(only if -latches error, the default)");
+			else if (latches == "error")
+				run("check -latchonly -assert");
 			run("techmap -map +/nanoxplore/latches_map.v");
 			run("techmap -map +/nanoxplore/cells_map.v");
 			run("opt_expr -undriven -mux_undef");
diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc
index 4458fdea5..322c947a2 100644
--- a/techlibs/quicklogic/synth_quicklogic.cc
+++ b/techlibs/quicklogic/synth_quicklogic.cc
@@ -331,12 +331,9 @@ struct SynthQuickLogicPass : public ScriptPass {
 
 		if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
 			if (help_mode)
-				run("check -assert", "(only if -latches error, the default)");
-			else if (latches == "error") {
-				active_design->scratchpad_set_bool("check.latchonly", true);
-				run("check -assert");
-				active_design->scratchpad_unset("check.latchonly");
-			}
+				run("check -latchonly -assert", "(only if -latches error, the default)");
+			else if (latches == "error")
+				run("check -latchonly -assert");
 			run("techmap -map " + lib_path + family + "/latches_map.v");
 			if (abc9) {
 				run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");
diff --git a/tests/various/check_nolatches.ys b/tests/various/check_nolatches.ys
index 9655dcd5c..927d35c7b 100644
--- a/tests/various/check_nolatches.ys
+++ b/tests/various/check_nolatches.ys
@@ -40,8 +40,7 @@ assign y = u;
 endmodule
 EOT
 proc
-scratchpad -set check.latchonly 1
 logger -expect warning "is a latch of type" 1
 logger -expect warning "used but has no driver" 0
 logger -expect error "Found 1 problems in" 1
-check -assert
+check -latchonly -assert