Add csa synth tests.

tests/csa_tree/abc_bench_add8.v

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+module abc_bench_add8(
+	input  [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule

tests/csa_tree/csa_tree_sim.ys

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+read_verilog sim_add4.v
+hierarchy -top sim_add4
+proc; opt_clean
+csa_tree
+opt_clean
+
+# 1 + 2 + 3 + 4 = 10
+sat -set a 1 -set b 2 -set c 3 -set d 4 -prove y 10
+
+# 0 + 0 + 0 + 0 = 0
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+
+# 255 + 1 + 0 + 0 = 0
+sat -set a 255 -set b 1 -set c 0 -set d 0 -prove y 0
+
+# 100 + 50 + 25 + 25 = 200
+sat -set a 100 -set b 50 -set c 25 -set d 25 -prove y 200
+
+# 255 + 255 + 255 + 255 = 252
+sat -set a 255 -set b 255 -set c 255 -set d 255 -prove y 252
+
+log "ok"
+

tests/csa_tree/csa_tree_synth.ys

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+# Baseline: no csa_tree
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+
+# Baseline synth
+techmap
+abc -g AND,OR,XOR
+opt_clean
+stat
+design -save baseline
+
+# With csa_tree
+design -reset
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+csa_tree
+techmap
+abc -g AND,OR,XOR
+opt_clean
+stat
+
+select -assert-max 250 t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NOT_ %u
+design -save csa_result
+
+# Depth comparison via ABC
+design -reset
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+techmap
+abc -D 1
+stat
+log "baseline depth mapping complete"
+
+design -reset
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+csa_tree
+techmap
+abc -D 1
+stat
+log "CSA depth mapping complete"

tests/csa_tree/sim_add4.v

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+module sim_add4(
+	input  [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule