From 8d0ecbcdc04d91c98b7e323b62b2ed2289b77fc3 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Fri, 13 Mar 2026 12:23:26 +0100
Subject: [PATCH] Add csa synth tests.

---
 tests/csa_tree/abc_bench_add8.v  |  6 +++++
 tests/csa_tree/csa_tree_sim.ys   | 23 ++++++++++++++++
 tests/csa_tree/csa_tree_synth.ys | 45 ++++++++++++++++++++++++++++++++
 tests/csa_tree/sim_add4.v        |  6 +++++
 4 files changed, 80 insertions(+)
 create mode 100644 tests/csa_tree/abc_bench_add8.v
 create mode 100644 tests/csa_tree/csa_tree_sim.ys
 create mode 100644 tests/csa_tree/csa_tree_synth.ys
 create mode 100644 tests/csa_tree/sim_add4.v

diff --git a/tests/csa_tree/abc_bench_add8.v b/tests/csa_tree/abc_bench_add8.v
new file mode 100644
index 000000000..7e61007c5
--- /dev/null
+++ b/tests/csa_tree/abc_bench_add8.v
@@ -0,0 +1,6 @@
+module abc_bench_add8(
+	input  [7:0] a, b, c, d, e, f, g, h,
+	output [7:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
diff --git a/tests/csa_tree/csa_tree_sim.ys b/tests/csa_tree/csa_tree_sim.ys
new file mode 100644
index 000000000..5a571c268
--- /dev/null
+++ b/tests/csa_tree/csa_tree_sim.ys
@@ -0,0 +1,23 @@
+read_verilog sim_add4.v
+hierarchy -top sim_add4
+proc; opt_clean
+csa_tree
+opt_clean
+
+# 1 + 2 + 3 + 4 = 10
+sat -set a 1 -set b 2 -set c 3 -set d 4 -prove y 10
+
+# 0 + 0 + 0 + 0 = 0
+sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
+
+# 255 + 1 + 0 + 0 = 0
+sat -set a 255 -set b 1 -set c 0 -set d 0 -prove y 0
+
+# 100 + 50 + 25 + 25 = 200
+sat -set a 100 -set b 50 -set c 25 -set d 25 -prove y 200
+
+# 255 + 255 + 255 + 255 = 252
+sat -set a 255 -set b 255 -set c 255 -set d 255 -prove y 252
+
+log "ok"
+
diff --git a/tests/csa_tree/csa_tree_synth.ys b/tests/csa_tree/csa_tree_synth.ys
new file mode 100644
index 000000000..e03580217
--- /dev/null
+++ b/tests/csa_tree/csa_tree_synth.ys
@@ -0,0 +1,45 @@
+# Baseline: no csa_tree
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+
+# Baseline synth
+techmap
+abc -g AND,OR,XOR
+opt_clean
+stat
+design -save baseline
+
+# With csa_tree
+design -reset
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+csa_tree
+techmap
+abc -g AND,OR,XOR
+opt_clean
+stat
+
+select -assert-max 250 t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NOT_ %u
+design -save csa_result
+
+# Depth comparison via ABC
+design -reset
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+techmap
+abc -D 1
+stat
+log "baseline depth mapping complete"
+
+design -reset
+read_verilog abc_bench_add8.v
+hierarchy -top abc_bench_add8
+proc; opt
+csa_tree
+techmap
+abc -D 1
+stat
+log "CSA depth mapping complete"
diff --git a/tests/csa_tree/sim_add4.v b/tests/csa_tree/sim_add4.v
new file mode 100644
index 000000000..589044889
--- /dev/null
+++ b/tests/csa_tree/sim_add4.v
@@ -0,0 +1,6 @@
+module sim_add4(
+	input  [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule