Add structural tests for csa_tree.

Makefile

@@ -953,6 +953,7 @@ MK_TEST_DIRS += tests/verilog
 
 # Tests that don't generate .mk
 SH_TEST_DIRS =
+SH_TEST_DIRS += tests/csa_tree
 SH_TEST_DIRS += tests/simple
 SH_TEST_DIRS += tests/simple_abc9
 SH_TEST_DIRS += tests/hana

tests/csa_tree/add_1bit.v

@@ -0,0 +1,9 @@
+// edge case for carry shifting
+
+module add_1bit(
+	input  a, b, c,
+	output [1:0] y
+);
+	assign y = a + b + c;
+endmodule
+

tests/csa_tree/add_chain_16.v

@@ -0,0 +1,7 @@
+module add_chain_16(
+	input  [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
+	input  [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
+	output [15:0] y
+);
+	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
+endmodule

tests/csa_tree/add_chain_2_neg.v

@@ -0,0 +1,8 @@
+// Shouldnt generate csa tree
+
+module add_chain_2(
+	input  [7:0] a, b,
+	output [7:0] y
+);
+	assign y = a + b;
+endmodule

tests/csa_tree/add_chain_3.v

@@ -0,0 +1,9 @@
+// Min chain len
+
+module add_chain_3(
+	input  [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a + b + c;
+endmodule
+

tests/csa_tree/add_chain_5.v

@@ -0,0 +1,7 @@
+module add_chain_5(
+	input  [11:0] a, b, c, d, e,
+	output [11:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+

tests/csa_tree/add_chain_8.v

@@ -0,0 +1,7 @@
+module add_chain_8(
+	input  [15:0] a, b, c, d, e, f, g, h,
+	output [15:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+

tests/csa_tree/add_mixed_widths.v

@@ -0,0 +1,10 @@
+module add_mixed_widths(
+	input  [7:0]  a,
+	input  [3:0]  b,
+	input  [15:0] c,
+	input  [7:0]  d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+

tests/csa_tree/add_multi_fanout.v

@@ -0,0 +1,10 @@
+module add_multi_fanout(
+	input  [7:0] a, b, c,
+	output [7:0] mid,
+	output [7:0] y
+);
+	wire [7:0] ab = a + b;
+	assign mid = ab;
+	assign y   = ab + c;
+endmodule
+

tests/csa_tree/add_signed.v

@@ -0,0 +1,6 @@
+module add_signed(
+	input  signed [7:0] a, b, c, d,
+	output signed [9:0] y
+);
+	assign y = a + b + c + d;
+endmodule

tests/csa_tree/add_two_chains.v

@@ -0,0 +1,9 @@
+module add_two_chains(
+	input  [7:0] a, b, c, d,
+	input  [7:0] e, f, g, h,
+	output [7:0] y1,
+	output [7:0] y2
+);
+	assign y1 = a + b + c + d;
+	assign y2 = e + f + g + h;
+endmodule

tests/csa_tree/add_wide_output.v

@@ -0,0 +1,6 @@
+module add_wide_output(
+	input  [7:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule

tests/csa_tree/add_with_const.v

@@ -0,0 +1,7 @@
+module add_with_const(
+	input  [7:0] a, b, c,
+	output [7:0] y
+);
+	assign y = a + b + c + 8'd42;
+endmodule
+

tests/csa_tree/csa_tree_16input.ys

@@ -0,0 +1,8 @@
+read_verilog add_chain_16.v
+hierarchy -auto-top
+proc; opt_clean
+csa_tree
+stat
+
+select -assert-min 5 t:$fa
+select -assert-count 1 t:$add

tests/csa_tree/csa_tree_1bit.ys

@@ -0,0 +1,8 @@
+# Test csa_tree with single-bit operands — carry shift edge case
+
+read_verilog add_1bit.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+

tests/csa_tree/csa_tree_2input_neg.ys

@@ -0,0 +1,11 @@
+# Test csa_tree on 2-operand — should not trigger
+
+read_verilog add_chain_2_neg.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-none t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/csa_tree_3input.ys

@@ -0,0 +1,11 @@
+# Test csa_tree on 3-operand chain — minimal trigger case
+
+read_verilog add_chain_3.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-count 1 t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/csa_tree_5input.ys

@@ -0,0 +1,11 @@
+# Test csa_tree with 5 operands — tree with remainders
+
+read_verilog add_chain_5.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-min 2 t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/csa_tree_8input.ys

@@ -0,0 +1,9 @@
+read_verilog add_chain_8.v
+hierarchy -auto-top
+proc; opt_clean
+csa_tree
+stat
+
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/csa_tree_const.ys

@@ -0,0 +1,9 @@
+read_verilog add_with_const.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/csa_tree_fir.ys

@@ -0,0 +1,8 @@
+read_verilog fir_4tap.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt -async2sync csa_tree
+design -load postopt
+
+select -assert-min 1 t:$fa
+

tests/csa_tree/csa_tree_mixed_widths.ys

@@ -0,0 +1,9 @@
+read_verilog add_mixed_widths.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/csa_tree_multi_fanout.ys

@@ -0,0 +1,8 @@
+read_verilog add_multi_fanout.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-none t:$fa
+

tests/csa_tree/csa_tree_signed.ys

@@ -0,0 +1,9 @@
+read_verilog add_signed.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/csa_tree_two_chains.ys

@@ -0,0 +1,9 @@
+read_verilog add_two_chains.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-min 2 t:$fa
+select -assert-count 2 t:$add
+

tests/csa_tree/csa_tree_wide_output.ys

@@ -0,0 +1,9 @@
+read_verilog add_wide_output.v
+hierarchy -auto-top
+proc; opt_clean
+equiv_opt csa_tree
+design -load postopt
+
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+

tests/csa_tree/fir_4tap.v

@@ -0,0 +1,24 @@
+module fir_4tap(
+	input         clk,
+	input  [15:0] x,
+	input  [15:0] c0, c1, c2, c3,
+	output reg [31:0] y
+);
+	reg [15:0] x1, x2, x3;
+	always @(posedge clk) begin
+		x1 <= x;
+		x2 <= x1;
+		x3 <= x2;
+	end
+
+	wire [31:0] p0 = x  * c0;
+	wire [31:0] p1 = x1 * c1;
+	wire [31:0] p2 = x2 * c2;
+	wire [31:0] p3 = x3 * c3;
+
+	wire [31:0] sum = p0 + p1 + p2 + p3;
+
+	always @(posedge clk)
+		y <= sum;
+endmodule
+

tests/csa_tree/run-test.sh

@@ -0,0 +1,7 @@
+#!/usr/bin/env bash
+source ../common-env.sh
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done