mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-24 20:16:01 +00:00
Code Activity

Improve naming: big fix

Browse source
This commit is contained in:
Akash Levy 2024-11-11 17:06:11 -08:00
parent ea76abdaee
commit 894c9816d3
18 changed files with 205 additions and 155 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/pmgen/peepopt_muxadd.pmg
View file

@ -38,8 +38,11 @@ code
// Get mux signal
SigSpec mux_y = port(mux, \Y);
// SILIMATE: Alias cell to mux for mid wire
Cell *cell = mux;
// Create new mid wire
SigSpec mid = module->addWire(NEW_ID, GetSize(add_b));
SigSpec mid = module->addWire(NEW_ID2_SUFFIX("mid"), GetSize(add_b)); // SILIMATE: Improve the naming
// Rewire
mux->setPort(\A, Const(State::S0, GetSize(add_b)));

9
passes/pmgen/peepopt_shiftmul_left.pmg
View file

@ -78,6 +78,9 @@ endmatch
code
{
// SILIMATE: Alias cell to shift for wires
Cell *cell = shift;
if (mul_const.empty() || GetSize(mul_const) > 20)
reject;
@ -129,7 +132,7 @@ code
if (bit == SigBit(State::Sm))
padbits++;
SigSpec padwire = module->addWire(NEW_ID, padbits);
SigSpec padwire = module->addWire(NEW_ID2_SUFFIX("pad"), padbits); // SILIMATE: Improve the naming
for (int i = new_y.size() - 1; i >= 0; i--)
if (new_y[i] == SigBit(State::Sm)) {
@ -148,8 +151,8 @@ code
shift->setPort(\B, new_b);
shift->setParam(\B_WIDTH, GetSize(new_b));
} else {
SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1);
module->addNeg(NEW_ID, new_b, b_neg);
SigSpec b_neg = module->addWire(NEW_ID2_SUFFIX("b_neg"), GetSize(new_b) + 1); // SILIMATE: Improve the naming
module->addNeg(NEW_ID2_SUFFIX("neg"), new_b, b_neg, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
shift->setPort(\B, b_neg);
shift->setParam(\B_WIDTH, GetSize(b_neg));
}