From 894c9816d35781584320410361f0d9fda8f23230 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Mon, 11 Nov 2024 17:06:11 -0800 Subject: [PATCH] Improve naming: big fix --- frontends/blif/blifparse.cc | 24 +++---- frontends/verific/verific.cc | 6 +- kernel/yosys_common.h | 10 +++ passes/cmds/splitfanout.cc | 4 +- passes/memory/memory_map.cc | 13 ++-- passes/memory/memory_share.cc | 16 ++--- passes/opt/muxpack.cc | 3 +- passes/opt/opt_balance_tree.cc | 3 +- passes/opt/opt_dff.cc | 72 ++++++++++---------- passes/opt/opt_expr.cc | 94 +++++++++++++++++--------- passes/opt/opt_mem.cc | 2 +- passes/opt/opt_mem_feedback.cc | 8 +-- passes/pmgen/peepopt_muxadd.pmg | 5 +- passes/pmgen/peepopt_shiftmul_left.pmg | 9 ++- passes/techmap/abc.cc | 4 +- passes/techmap/bmuxmap.cc | 33 ++++----- passes/techmap/extract_reduce.cc | 6 +- passes/techmap/simplemap.cc | 48 ++++++------- 18 files changed, 205 insertions(+), 155 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index f6b894563..a6be17dcc 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -362,19 +362,19 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto no_latch_clock; if (!strcmp(edge, "re")) - cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDff(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); // SILIMATE: Improve the naming else if (!strcmp(edge, "fe")) - cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDff(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); // SILIMATE: Improve the naming else if (!strcmp(edge, "ah")) - cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDlatch(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); // SILIMATE: Improve the naming else if (!strcmp(edge, "al")) - cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDlatch(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); // SILIMATE: Improve the naming else { no_latch_clock: if (dff_name.empty()) { - cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q)); + cell = module->addFf(NEW_ABC_ID, blif_wire(d), blif_wire(q)); // SILIMATE: Improve the naming } else { - cell = module->addCell(NEW_ID, dff_name); + cell = module->addCell(NEW_ABC_ID, dff_name); // SILIMATE: Improve the naming cell->setPort(ID::D, blif_wire(d)); cell->setPort(ID::Q, blif_wire(q)); } @@ -393,7 +393,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto error; IdString celltype = RTLIL::escape_id(p); - RTLIL::Cell *cell = module->addCell(NEW_ID, celltype); + RTLIL::Cell *cell = module->addCell(NEW_ABC_ID, celltype); // SILIMATE: Improve the naming RTLIL::Module *cell_mod = design->module(celltype); dict> cell_wideports_cache; @@ -440,7 +440,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (it.second.count(idx)) sig.append(it.second.at(idx)); else - sig.append(module->addWire(NEW_ID)); + sig.append(module->addWire(NEW_ABC_ID)); // SILIMATE: Improve the naming } cell->setPort(it.first, sig); @@ -516,7 +516,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (sop_mode) { - sopcell = module->addCell(NEW_ID, ID($sop)); + sopcell = module->addCell(NEW_ABC_ID, ID($sop)); // SILIMATE: Improve the naming sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); sopcell->parameters[ID::DEPTH] = 0; sopcell->parameters[ID::TABLE] = RTLIL::Const(); @@ -532,7 +532,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool } else { - RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut)); + RTLIL::Cell *cell = module->addCell(NEW_ABC_ID, ID($lut)); // SILIMATE: Improve the naming cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); cell->setPort(ID::A, input_sig); @@ -583,8 +583,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool sopmode = (*output == '1'); if (!sopmode) { SigSpec outnet = sopcell->getPort(ID::Y); - SigSpec tempnet = module->addWire(NEW_ID); - module->addNotGate(NEW_ID, tempnet, outnet); + SigSpec tempnet = module->addWire(NEW_ABC_ID); // SILIMATE: Improve the naming + module->addNotGate(NEW_ABC_ID, tempnet, outnet); // SILIMATE: Improve the naming sopcell->setPort(ID::Y, tempnet); } } else diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 56f3fcf31..abb899640 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -227,10 +227,10 @@ bool is_blackbox(Netlist *nl) RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj) { - // SILIMATE: Use uniquified Verific ID as Yosys ID - // TODO: improve this + // SILIMATE: Uniquify by adding _ suffix std::string s = stringf("$%s", obj->Name()); - while (seen_ids.count(s)) s += stringf("$%d", autoidx++); + while (seen_ids.count(s + stringf("_ix%d", autoidx))) autoidx++; + s += stringf("_ix%d", autoidx++); seen_ids.insert(s); return s; } diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index ed41323b4..2a83b0e0d 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -358,6 +358,16 @@ RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std: YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__) #define NEW_ID_SUFFIX(suffix) \ YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix) +#define NEW_ID2 \ + module->uniquify(cell->name.str()) +#define NEW_ID2_SUFFIX(suffix) \ + module->uniquify(cell->name.str() + "_" + suffix) +#define NEW_ID2_SUFFIX2(suffix) \ + module->uniquify(cell_name.str() + "_" + suffix) +#define NEW_ABC_ID \ + module->uniquify(IdString("\\boolopt")) +#define NEW_MEM_ID_SUFFIX(suffix) \ + module->uniquify(mem.mem->name.str() + "_" + suffix) // Create a statically allocated IdString object, using for example ID::A or ID($add). // diff --git a/passes/cmds/splitfanout.cc b/passes/cmds/splitfanout.cc index c1630fe5e..5dff2b6ad 100644 --- a/passes/cmds/splitfanout.cc +++ b/passes/cmds/splitfanout.cc @@ -157,7 +157,7 @@ struct SplitfanoutWorker // Connect the new cell to the user if (std::get<1>(bit_user) == IdString()) { // is wire Wire *old_wire = module->wire(std::get<0>(bit_user)); - Wire *new_wire = module->addWire(NEW_ID, old_wire); + Wire *new_wire = module->addWire(NEW_ID2_SUFFIX("splfo"), old_wire); // SILIMATE: Improve the naming module->swap_names(old_wire, new_wire); old_wire->port_input = false; old_wire->port_output = false; @@ -165,7 +165,7 @@ struct SplitfanoutWorker new_cell->setPort(outport, sig); } else { - Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig)); + Wire *new_wire = module->addWire(NEW_ID2_SUFFIX("splfo"), GetSize(outsig)); // SILIMATE: Improve the naming Cell *target_cell = module->cell(std::get<0>(bit_user)); SigSpec sig = target_cell->getPort(std::get<1>(bit_user)); sig.replace(std::get<2>(bit_user), new_wire); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index d1dd0fd88..ba741d4ea 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -82,19 +82,18 @@ struct MemoryMapWorker return sstr.str(); } - RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val) + RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val, Module *module, Mem &mem) { std::pair key(addr_sig, addr_val); log_assert(GetSize(addr_sig) == GetSize(addr_val)); - if (decoder_cache.count(key) == 0) { if (GetSize(addr_sig) < 2) { - decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val); + decoder_cache[key] = module->Eq(NEW_MEM_ID_SUFFIX("addr_decode"), addr_sig, addr_val, false, mem.get_src_attribute()); // SILIMATE: Improve the naming } else { int split_at = GetSize(addr_sig) / 2; - RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at)); - RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at)); - decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq); + RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at), module, mem); + RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at), module, mem); + decoder_cache[key] = module->And(NEW_MEM_ID_SUFFIX("addr_decode"), left_eq, right_eq, false, mem.get_src_attribute()); // SILIMATE: Improve the naming } } @@ -329,7 +328,7 @@ struct MemoryMapWorker { auto &port = mem.wr_ports[j]; RTLIL::SigSpec wr_addr = port.addr.extract_end(port.wide_log2); - RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(addr >> port.wide_log2, GetSize(wr_addr))); + RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(addr >> port.wide_log2, GetSize(wr_addr)), module, mem); int sub = addr & ((1 << port.wide_log2) - 1); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index a19807f22..5e47be18c 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -163,7 +163,7 @@ struct MemoryShareWorker port2.addr = addr2; mem.prepare_rd_merge(i, j, &initvals); mem.widen_prep(wide_log2); - SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2); + SigSpec new_data = module->addWire(NEW_MEM_ID_SUFFIX("data"), mem.width << wide_log2); // SILIMATE: Improve the naming module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2)); module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2)); for (int k = 0; k < wide_log2; k++) @@ -270,8 +270,8 @@ struct MemoryShareWorker port1.data.replace(pos, port2.data.extract(pos, width)); new_en = port2.en[pos]; } else { - port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos])); - new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]); + port1.data.replace(pos, module->Mux(NEW_MEM_ID_SUFFIX("data_mux"), port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos], mem.get_src_attribute())); // SILIMATE: Improve the naming + new_en = module->Or(NEW_MEM_ID_SUFFIX("en"), port1.en[pos], port2.en[pos], false, mem.get_src_attribute()); // SILIMATE: Improve the naming } for (int k = pos; k < epos; k++) port1.en[k] = new_en; @@ -423,21 +423,21 @@ struct MemoryShareWorker RTLIL::SigSpec this_data = port2.data; std::vector this_en = modwalker.sigmap(port2.en); - RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); + RTLIL::SigBit this_en_active = module->ReduceOr(NEW_MEM_ID_SUFFIX("en_active"), this_en, false, mem.get_src_attribute()); // SILIMATE: Improve the naming if (GetSize(last_addr) < GetSize(this_addr)) last_addr.extend_u0(GetSize(this_addr)); else this_addr.extend_u0(GetSize(last_addr)); - SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active); + SigSpec new_addr = module->Mux(NEW_MEM_ID_SUFFIX("addr"), last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active, mem.get_src_attribute()); // SILIMATE: Improve the naming port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)}); - port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active); + port1.data = module->Mux(NEW_MEM_ID_SUFFIX("data"), last_data, this_data, this_en_active, mem.get_src_attribute()); // SILIMATE: Improve the naming std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; - RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0); + RTLIL::Wire *grouped_en = module->addWire(NEW_MEM_ID_SUFFIX("grouped_en"), 0); // SILIMATE: Improve the naming for (int j = 0; j < int(this_en.size()); j++) { std::pair key(last_en[j], this_en[j]); @@ -450,7 +450,7 @@ struct MemoryShareWorker en.append(RTLIL::SigSpec(grouped_en, groups_en[key])); } - module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); + module->addMux(NEW_MEM_ID_SUFFIX("en_mux"), grouped_last_en, grouped_this_en, this_en_active, grouped_en, mem.get_src_attribute()); // SILIMATE: Improve the naming port1.en = en; port2.removed = true; diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 26ea03391..dc00440c0 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -276,6 +276,7 @@ struct MuxpackWorker for (int i = 1; i < cases; i++) { Cell* prev_cell = chain[cursor+i-1]; Cell* cursor_cell = chain[cursor+i]; + Cell* cell = cursor_cell; // SILIMATE: Set cell to cursor cell for better naming if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) { b_sig.append(cursor_cell->getPort(ID::B)); s_sig.append(cursor_cell->getPort(ID::S)); @@ -283,7 +284,7 @@ struct MuxpackWorker else { log_assert(cursor_cell->type == ID($mux)); b_sig.append(cursor_cell->getPort(ID::A)); - s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S))); + s_sig.append(module->LogicNot(NEW_ID2_SUFFIX("sel"), cursor_cell->getPort(ID::S), false, cell->get_src_attribute())); // SILIMATE: Improve the naming } remove_cells.insert(cursor_cell); } diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 1f902a2b0..7a53e600f 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -207,6 +207,7 @@ struct OptBalanceTreeWorker { // Get mid, midnext (at index mid+1) and end of chain Cell *mid_cell = chain[GetSize(chain) / 2]; + Cell *cell = mid_cell; // SILIMATE: Set cell to mid_cell for better naming Cell *midnext_cell = chain[GetSize(chain) / 2 + 1]; Cell *end_cell = chain.back(); log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n", @@ -227,7 +228,7 @@ struct OptBalanceTreeWorker { SigSpec end_y_sig = sigmap(end_cell->getPort(ID::Y)); // Create new mid wire - Wire *mid_wire = module->addWire(NEW_ID, GetSize(end_y_sig)); + Wire *mid_wire = module->addWire(NEW_ID2_SUFFIX("mid"), GetSize(end_y_sig)); // SILIMATE: Improve the naming // Perform rotation mid_cell->setPort(mid_non_chain_port, mid_wire); diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 8539432c0..fc0637bda 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -175,7 +175,7 @@ struct OptDffWorker // TBD } - ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates) + ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates, Module *module, Cell *cell) { if (patterns.empty() && GetSize(ctrls) == 1) { return *ctrls.begin(); @@ -191,8 +191,8 @@ struct OptDffWorker s2.append(it.second); } - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y); + RTLIL::SigSpec y = module->addWire(NEW_ID2_SUFFIX("pat_y")); // SILIMATE: Improve the naming + RTLIL::Cell *c = module->addNe(NEW_ID2_SUFFIX("pat_ne"), s1, s2, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming if (make_gates) { simplemap(module, c); @@ -205,9 +205,9 @@ struct OptDffWorker if (item.second) or_input.append(item.first); else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); + or_input.append(module->NotGate(NEW_ID2_SUFFIX("ctrl_inv"), item.first, cell->get_src_attribute())); // SILIMATE: Improve the naming else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(module->Not(NEW_ID2_SUFFIX("ctrl_inv"), item.first, false, cell->get_src_attribute())); // SILIMATE: Improve the naming } if (GetSize(or_input) == 0) @@ -216,8 +216,8 @@ struct OptDffWorker if (GetSize(or_input) == 1) return ctrl_t(or_input, true); - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); + RTLIL::SigSpec y = module->addWire(NEW_ID2_SUFFIX("pat_logic_y")); // SILIMATE: Improve the naming + RTLIL::Cell *c = module->addReduceAnd(NEW_ID2_SUFFIX("pat_logic_reduce_and"), or_input, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming if (make_gates) { simplemap(module, c); @@ -227,7 +227,7 @@ struct OptDffWorker return ctrl_t(y, true); } - ctrl_t combine_resets(const ctrls_t &ctrls, bool make_gates) + ctrl_t combine_resets(const ctrls_t &ctrls, bool make_gates, Module *module, Cell *cell) { if (GetSize(ctrls) == 1) { return *ctrls.begin(); @@ -245,13 +245,17 @@ struct OptDffWorker if (item.second == final_pol) or_input.append(item.first); else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); + or_input.append(module->NotGate(NEW_ID2_SUFFIX("comb_rst_inv"), item.first, cell->get_src_attribute())); // SILIMATE: Improve the naming else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(module->Not(NEW_ID2_SUFFIX("comb_rst_inv"), item.first, false, cell->get_src_attribute())); // SILIMATE: Improve the naming } - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y); + RTLIL::SigSpec y = module->addWire(NEW_ID2_SUFFIX("comb_rst_y")); // SILIMATE: Improve the naming + RTLIL::Cell *c; + if (final_pol) + c = module->addReduceOr(NEW_ID2_SUFFIX("comb_rst_reduce_or"), or_input, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming + else + c = module->addReduceAnd(NEW_ID2_SUFFIX("comb_rst_reduce_and"), or_input, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming if (make_gates) { simplemap(module, c); @@ -295,9 +299,9 @@ struct OptDffWorker if (!ff.pol_clr) { module->connect(ff.sig_q[i], ff.sig_clr[i]); } else if (ff.is_fine) { - module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + module->addNotGate(NEW_ID2_SUFFIX("aactive_set"), ff.sig_clr[i], ff.sig_q[i], cell->get_src_attribute()); // SILIMATE: Improve the naming } else { - module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + module->addNot(NEW_ID2_SUFFIX("aactive_set"), ff.sig_clr[i], ff.sig_q[i], false, cell->get_src_attribute()); // SILIMATE: Improve the naming } log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", i, log_id(cell), log_id(cell->type), log_id(module)); @@ -396,34 +400,34 @@ struct OptDffWorker SigSpec tmp; if (ff.is_fine) { if (ff.pol_set) - tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set); + tmp = module->MuxGate(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, State::S1, ff.sig_set, cell->get_src_attribute()); // SILIMATE: Improve the naming else - tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set); + tmp = module->MuxGate(NEW_ID2_SUFFIX("aactive_aload"), State::S1, ff.sig_ad, ff.sig_set, cell->get_src_attribute()); // SILIMATE: Improve the naming if (ff.pol_clr) - module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); + module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), tmp, State::S0, ff.sig_clr, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming else - module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); + module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), State::S0, tmp, ff.sig_clr, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming } else { if (ff.pol_set) - tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set); + tmp = module->Or(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, ff.sig_set, false, cell->get_src_attribute()); // SILIMATE: Improve the naming else - tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set)); + tmp = module->Or(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, module->Not(NEW_ID2_SUFFIX("aactive_aload_inv"), ff.sig_set, false, cell->get_src_attribute())); // SILIMATE: Improve the naming if (ff.pol_clr) - module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q); + module->addAnd(NEW_ID2_SUFFIX("aactive_aload"), tmp, module->Not(NEW_ID2_SUFFIX("aactive_aload_inv"), ff.sig_clr, false, cell->get_src_attribute()), ff.sig_q); // SILIMATE: Improve the naming else - module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q); + module->addAnd(NEW_ID2_SUFFIX("aactive_aload"), tmp, ff.sig_clr, ff.sig_q, false, cell->get_src_attribute()); // SILIMATE: Improve the naming } } else if (ff.has_arst) { if (ff.is_fine) { if (ff.pol_arst) - module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q); + module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming else - module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q); + module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming } else { if (ff.pol_arst) - module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q); + module->addMux(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming else - module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q); + module->addMux(NEW_ID2_SUFFIX("aactive_aload"), ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming } } else { module->connect(ff.sig_q, ff.sig_ad); @@ -539,20 +543,20 @@ struct OptDffWorker if (ff.has_ce && ff.ce_over_srst) { if (!ff.pol_ce) { if (ff.is_fine) - ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce); + ff.sig_ce = module->NotGate(NEW_ID2_SUFFIX("ce"), ff.sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming else - ff.sig_ce = module->Not(NEW_ID, ff.sig_ce); + ff.sig_ce = module->Not(NEW_ID2_SUFFIX("ce"), ff.sig_ce, false, cell->get_src_attribute()); // SILIMATE: Improve the naming } if (!ff.pol_srst) { if (ff.is_fine) - ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst); + ff.sig_srst = module->NotGate(NEW_ID2_SUFFIX("srst"), ff.sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming else - ff.sig_srst = module->Not(NEW_ID, ff.sig_srst); + ff.sig_srst = module->Not(NEW_ID2_SUFFIX("srst"), ff.sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming } if (ff.is_fine) - ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst); + ff.sig_ce = module->AndGate(NEW_ID2_SUFFIX("ce"), ff.sig_ce, ff.sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming else - ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst); + ff.sig_ce = module->And(NEW_ID2_SUFFIX("ce"), ff.sig_ce, ff.sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming ff.pol_ce = true; } else { ff.pol_ce = ff.pol_srst; @@ -636,7 +640,7 @@ struct OptDffWorker int j = it.second[i]; new_ff.val_srst.bits().push_back(val_srst[j]); } - ctrl_t srst = combine_resets(it.first, ff.is_fine); + ctrl_t srst = combine_resets(it.first, ff.is_fine, module, cell); new_ff.has_srst = true; new_ff.sig_srst = srst.first; @@ -700,7 +704,7 @@ struct OptDffWorker for (auto &it : groups) { FfData new_ff = ff.slice(it.second); - ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine); + ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine, module, cell); new_ff.has_ce = true; new_ff.sig_ce = en.first; diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index ac4a65156..573143033 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -202,7 +202,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ if (grouped_bits[i].empty()) continue; - RTLIL::SigSpec new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i])); + RTLIL::SigSpec new_y = module->addWire(NEW_ID2_SUFFIX("grp_y"), GetSize(grouped_bits[i])); // SILIMATE: Improve the naming RTLIL::SigSpec new_a, new_b; RTLIL::SigSig new_conn; @@ -247,9 +247,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ else if (new_a[i] == State::S0 || new_a[i] == State::S1) { undef_a.append(new_a[i]); if (cell->type == ID($xor)) - undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]); + undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID2_SUFFIX("grp_undef_b"), new_b[i], false, cell->get_src_attribute()).as_bit() : new_b[i]); // SILIMATE: Improve the naming else if (cell->type == ID($xnor)) - undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit()); + undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID2_SUFFIX("grp_undef_b"), new_b[i], false, cell->get_src_attribute()).as_bit()); // SILIMATE: Improve the naming else log_abort(); undef_y.append(new_y[i]); } @@ -272,8 +272,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ new_y = std::move(def_y); } - - RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); + // SILIMATE: New cell takes on old cell's name + RTLIL::IdString cell_name = cell->name; + module->rename(cell->name, NEW_ID); + RTLIL::Cell *c = module->addCell(cell_name, cell->type); + c->set_src_attribute(cell->get_src_attribute()); c->setPort(ID::A, new_a); c->parameters[ID::A_WIDTH] = new_a.size(); @@ -612,9 +615,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover("opt.opt_expr.xor_buffer"); SigSpec sig_y; if (cell->type == ID($xor)) - sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a); + sig_y = (sig_b == State::S1 ? module->Not(NEW_ID2_SUFFIX("xor_inv"), sig_a, false, cell->get_src_attribute()).as_bit() : sig_a); // SILIMATE: Improve the naming else if (cell->type == ID($_XOR_)) - sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); + sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID2_SUFFIX("xor_inv"), sig_a, cell->get_src_attribute()) : sig_a); // SILIMATE: Improve the naming else log_abort(); replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y); goto next_cell; @@ -623,12 +626,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover("opt.opt_expr.xnor_buffer"); SigSpec sig_y; if (cell->type == ID($xnor)) { - sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit()); + sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID2_SUFFIX("xnor_inv"), sig_a, false, cell->get_src_attribute()).as_bit()); // SILIMATE: Improve the naming int width = cell->getParam(ID::Y_WIDTH).as_int(); sig_y.append(RTLIL::Const(State::S1, width-1)); } else if (cell->type == ID($_XNOR_)) - sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); + sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID2_SUFFIX("xnor_inv"), sig_a, cell->get_src_attribute())); // SILIMATE: Improve the naming else log_abort(); replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y); goto next_cell; @@ -693,12 +696,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec y_new_0, y_new_1, y_new_x; + // SILIMATE: New cell takes on old cell's name + RTLIL::IdString cell_name = cell->name; + module->rename(cell->name, NEW_ID); + if (cell->type == ID($and)) { if (!y_group_0.empty()) y_new_0 = Const(State::S0, GetSize(y_group_0)); if (!y_group_1.empty()) y_new_1 = b_group_1; if (!y_group_x.empty()) { if (keepdc) - y_new_x = module->And(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); + y_new_x = module->And(cell_name, Const(State::Sx, GetSize(y_group_x)), b_group_x, false, cell->get_src_attribute()); // SILIMATE: Improve the naming else y_new_x = Const(State::S0, GetSize(y_group_x)); } @@ -707,16 +714,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!y_group_1.empty()) y_new_1 = Const(State::S1, GetSize(y_group_1)); if (!y_group_x.empty()) { if (keepdc) - y_new_x = module->Or(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); + y_new_x = module->Or(cell_name, Const(State::Sx, GetSize(y_group_x)), b_group_x, false, cell->get_src_attribute()); // SILIMATE: Improve the naming else y_new_x = Const(State::S1, GetSize(y_group_x)); } } else if (cell->type.in(ID($xor), ID($xnor))) { if (!y_group_0.empty()) y_new_0 = b_group_0; - if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID, b_group_1); + if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID2_SUFFIX2("inv"), b_group_1, false, cell->get_src_attribute()); // SILIMATE: Improve the naming if (!y_group_x.empty()) { if (keepdc) - y_new_x = module->Xor(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x); + y_new_x = module->Xor(cell_name, Const(State::Sx, GetSize(y_group_x)), b_group_x, false, cell->get_src_attribute()); // SILIMATE: Improve the naming else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor y_new_x = Const(State::Sx, GetSize(y_group_x)); } @@ -762,6 +769,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } else if (sig_a.is_fully_def() || sig_b.is_fully_def()) { + // SILIMATE: New cell takes on old cell's name + RTLIL::IdString cell_name = cell->name; + module->rename(cell->name, NEW_ID); + bool flip = !sig_a.is_fully_def(); if (flip) std::swap(sig_a, sig_b); @@ -779,11 +790,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec y_new_0, y_new_1; if (flip) { - if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, module->Not(NEW_ID, s_group_0)); - if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, s_group_1); + if (!y_group_0.empty()) y_new_0 = module->And(cell_name, b_group_0, module->Not(NEW_ID2_SUFFIX2("inv"), s_group_0, false, cell->get_src_attribute()), false, cell->get_src_attribute()); // SILIMATE: Improve the naming + if (!y_group_1.empty()) y_new_1 = module->Or(cell_name, b_group_1, s_group_1, false, cell->get_src_attribute()); // SILIMATE: Improve the naming } else { - if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, s_group_0); - if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, module->Not(NEW_ID, s_group_1)); + if (!y_group_0.empty()) y_new_0 = module->And(cell_name, b_group_0, s_group_0, false, cell->get_src_attribute()); // SILIMATE: Improve the naming + if (!y_group_1.empty()) y_new_1 = module->Or(cell_name, b_group_1, module->Not(NEW_ID2_SUFFIX2("inv"), s_group_1, false, cell->get_src_attribute()), false, cell->get_src_attribute()); // SILIMATE: Improve the naming } module->connect(y_group_0, y_new_0); @@ -996,12 +1007,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigBit a = sig_a[i]; if (b == ((bi ^ ci) ? State::S1 : State::S0)) { module->connect(sig_y[i], a); - module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a); + module->connect(sig_x[i], ci ? module->Not(NEW_ID2_SUFFIX("sig_x_inv"), a, false, cell->get_src_attribute()).as_bit() : a); // SILIMATE: Improve the naming module->connect(sig_co[i], ci ? State::S1 : State::S0); } else if (a == (ci ? State::S1 : State::S0)) { - module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b); - module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b); + module->connect(sig_y[i], bi ? module->Not(NEW_ID2_SUFFIX("sig_y_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming + module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID2_SUFFIX("sig_x_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming module->connect(sig_co[i], ci ? State::S1 : State::S0); } else @@ -1418,7 +1429,7 @@ skip_fine_alu: /* sub, b is 0 */ RTLIL::SigSpec a = cell->getPort(ID::A); a.extend_u0(y_width, is_signed); - module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a)); + module->connect(cell->getPort(ID::X), module->Not(NEW_ID2_SUFFIX("sig_ci_inv"), a, false, cell->get_src_attribute())); // SILIMATE: Improve the naming module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width)); } else { /* add */ @@ -1834,13 +1845,13 @@ skip_identity: // Truncating division is the same as flooring division, except when // the result is negative and there is a remainder - then trunc = floor + 1 if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) { - Wire *flooring = module->addWire(NEW_ID, sig_y.size()); + Wire *flooring = module->addWire(NEW_ID2_SUFFIX("flooring"), sig_y.size()); // SILIMATE: Improve the naming cell->setPort(ID::Y, flooring); SigSpec a_sign = sig_a[sig_a.size()-1]; - SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp)); - SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero); - module->addAdd(NEW_ID, flooring, should_add, sig_y); + SigSpec rem_nonzero = module->ReduceOr(NEW_ID2_SUFFIX("rem_nonzero"), sig_a.extract(0, exp)); // SILIMATE: Improve the naming + SigSpec should_add = module->And(NEW_ID2_SUFFIX("should_add"), a_sign, rem_nonzero); // SILIMATE: Improve the naming + module->addAdd(NEW_ID2_SUFFIX("add"), flooring, should_add, sig_y); // SILIMATE: Improve the naming } cell->check(); @@ -1862,11 +1873,11 @@ skip_identity: SigSpec truncating = sig_a.extract(0, exp); SigSpec a_sign = sig_a[sig_a.size()-1]; - SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp)); - SigSpec extend_bit = module->And(NEW_ID, a_sign, rem_nonzero); + SigSpec rem_nonzero = module->ReduceOr(NEW_ID2_SUFFIX("rem_nonzero"), sig_a.extract(0, exp), false, cell->get_src_attribute()); // SILIMATE: Improve the naming + SigSpec extend_bit = module->And(NEW_ID2_SUFFIX("extend_bit"), a_sign, rem_nonzero, false, cell->get_src_attribute()); // SILIMATE: Improve the naming truncating.append(extend_bit); - module->addPos(NEW_ID, truncating, sig_y, true); + module->addPos(NEW_ID2_SUFFIX("pos"), truncating, sig_y, true, cell->get_src_attribute()); // SILIMATE: Improve the naming } else { @@ -1949,7 +1960,12 @@ skip_identity: int sz = cur - prev; bool last = cur == GetSize(sig_y); - RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); + // SILIMATE: New cell takes on old cell's name + RTLIL::IdString cell_name = cell->name; + module->rename(cell->name, NEW_ID); + + RTLIL::Cell *c = module->addCell(cell_name, cell->type); // SILIMATE: Improve the naming + c->set_src_attribute(cell->get_src_attribute()); c->setPort(ID::A, sig_a.extract(prev, sz)); c->setPort(ID::B, sig_b.extract(prev, sz)); c->setPort(ID::BI, sig_bi); @@ -1959,7 +1975,7 @@ skip_identity: RTLIL::SigSpec new_co = sig_co.extract(prev, sz); if (p.second != State::Sx) { module->connect(new_co[sz-1], p.second); - RTLIL::Wire *dummy = module->addWire(NEW_ID); + RTLIL::Wire *dummy = module->addWire(NEW_ID2_SUFFIX2("dummy")); // SILIMATE: Improve the naming new_co[sz-1] = dummy; } c->setPort(ID::CO, new_co); @@ -2124,16 +2140,24 @@ skip_alu_split: if (cmp_type == ID($lt)) { + // SILIMATE: New cell takes on old cell's name + RTLIL::IdString cell_name = cell->name; + module->rename(cell->name, NEW_ID); + condition = stringf("unsigned X<%s", log_signal(const_sig)); replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot); - module->addLogicNot(NEW_ID, var_high_sig, cell->getPort(ID::Y)); + module->addLogicNot(cell_name, var_high_sig, cell->getPort(ID::Y), false, cell->get_src_attribute()); // SILIMATE: Improve the naming remove = true; } if (cmp_type == ID($ge)) { + // SILIMATE: New cell takes on old cell's name + RTLIL::IdString cell_name = cell->name; + module->rename(cell->name, NEW_ID); + condition = stringf("unsigned X>=%s", log_signal(const_sig)); replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot); - module->addReduceOr(NEW_ID, var_high_sig, cell->getPort(ID::Y)); + module->addReduceOr(cell_name, var_high_sig, cell->getPort(ID::Y), false, cell->get_src_attribute()); // SILIMATE: Improve the naming remove = true; } } @@ -2173,9 +2197,13 @@ skip_alu_split: } if (const_sig.is_fully_zero() && cmp_type == ID($ge)) { + // SILIMATE: New cell takes on old cell's name + RTLIL::IdString cell_name = cell->name; + module->rename(cell->name, NEW_ID); + condition = "signed X>=0"; replacement = stringf("X[%d]", var_width - 1); - module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y)); + module->addLogicNot(cell_name, var_sig[var_width - 1], cell->getPort(ID::Y), false, cell->get_src_attribute()); // SILIMATE: Improve the naming remove = true; } } diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index f8354c960..741708101 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -125,7 +125,7 @@ struct OptMemPass : public Pass { module->connect(port.data[bidx], bit); } else { // The FF will most likely be redundant, but it's up to opt_dff to deal with this. - FfData ff(module, &initvals, NEW_ID); + FfData ff(module, &initvals, NEW_MEM_ID_SUFFIX("ffdata")); // SILIMATE: Improve the naming ff.width = 1; ff.has_clk = true; ff.sig_clk = port.clk; diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index 20a2a79ed..b075fa8fd 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -106,7 +106,7 @@ struct OptMemFeedbackWorker find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, wrport_idx, data_bit_idx, paths); } - RTLIL::SigBit conditions_to_logic(pool> &conditions, SigBit olden) + RTLIL::SigBit conditions_to_logic(pool> &conditions, SigBit olden, Module *module, Mem &mem) { auto key = make_pair(conditions, olden); @@ -120,7 +120,7 @@ struct OptMemFeedbackWorker sig1.append(it.first); sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0); } - terms.append(module->Ne(NEW_ID, sig1, sig2)); + terms.append(module->Ne(NEW_MEM_ID_SUFFIX("cond_ne"), sig1, sig2, false, mem.get_src_attribute())); // SILIMATE: Improve the naming } if (olden != State::S1) @@ -130,7 +130,7 @@ struct OptMemFeedbackWorker terms = State::S1; if (GetSize(terms) > 1) - terms = module->ReduceAnd(NEW_ID, terms); + terms = module->ReduceAnd(NEW_MEM_ID_SUFFIX("cond_reduce_and"), terms, false, mem.get_src_attribute()); // SILIMATE: Improve the naming return conditions_logic_cache[key] = terms; } @@ -255,7 +255,7 @@ struct OptMemFeedbackWorker int bit = it.first.second; auto &port = mem.wr_ports[wrport_idx]; - port.en[bit] = conditions_to_logic(it.second, port.en[bit]); + port.en[bit] = conditions_to_logic(it.second, port.en[bit], module, mem); log(" Port %d bit %d: added enable logic for %d different cases.\n", wrport_idx, bit, GetSize(it.second)); } diff --git a/passes/pmgen/peepopt_muxadd.pmg b/passes/pmgen/peepopt_muxadd.pmg index 435f09599..0aff8ba64 100644 --- a/passes/pmgen/peepopt_muxadd.pmg +++ b/passes/pmgen/peepopt_muxadd.pmg @@ -38,8 +38,11 @@ code // Get mux signal SigSpec mux_y = port(mux, \Y); + // SILIMATE: Alias cell to mux for mid wire + Cell *cell = mux; + // Create new mid wire - SigSpec mid = module->addWire(NEW_ID, GetSize(add_b)); + SigSpec mid = module->addWire(NEW_ID2_SUFFIX("mid"), GetSize(add_b)); // SILIMATE: Improve the naming // Rewire mux->setPort(\A, Const(State::S0, GetSize(add_b))); diff --git a/passes/pmgen/peepopt_shiftmul_left.pmg b/passes/pmgen/peepopt_shiftmul_left.pmg index 607f8368c..930cadb91 100644 --- a/passes/pmgen/peepopt_shiftmul_left.pmg +++ b/passes/pmgen/peepopt_shiftmul_left.pmg @@ -78,6 +78,9 @@ endmatch code { + // SILIMATE: Alias cell to shift for wires + Cell *cell = shift; + if (mul_const.empty() || GetSize(mul_const) > 20) reject; @@ -129,7 +132,7 @@ code if (bit == SigBit(State::Sm)) padbits++; - SigSpec padwire = module->addWire(NEW_ID, padbits); + SigSpec padwire = module->addWire(NEW_ID2_SUFFIX("pad"), padbits); // SILIMATE: Improve the naming for (int i = new_y.size() - 1; i >= 0; i--) if (new_y[i] == SigBit(State::Sm)) { @@ -148,8 +151,8 @@ code shift->setPort(\B, new_b); shift->setParam(\B_WIDTH, GetSize(new_b)); } else { - SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1); - module->addNeg(NEW_ID, new_b, b_neg); + SigSpec b_neg = module->addWire(NEW_ID2_SUFFIX("b_neg"), GetSize(new_b) + 1); // SILIMATE: Improve the naming + module->addNeg(NEW_ID2_SUFFIX("neg"), new_b, b_neg, false, cell->get_src_attribute()); // SILIMATE: Improve the naming shift->setPort(\B, b_neg); shift->setParam(\B_WIDTH, GetSize(b_neg)); } diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 07f9ee45d..b0b849133 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -400,7 +400,7 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp auto sig = signal_list.at(sid); if (sig.bit.wire != nullptr) { - std::string s = stringf("$abc$%d$%s", map_autoidx, sig.bit.wire->name.c_str()+1); + std::string s = stringf("\\%s_ix%d", sig.bit.wire->name.c_str()+1, map_autoidx); // SILIMATE: Improve the naming if (sig.bit.wire->width != 1) s += stringf("[%d]", sig.bit.offset); if (isnew) @@ -413,7 +413,7 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp } } } - return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1); + return stringf("\\%s_ix%d", abc_name.c_str()+1, map_autoidx); // SILIMATE: Improve the naming } void dump_loop_graph(FILE *f, int &nr, dict> &edges, pool &workpool, std::vector &in_counts) diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc index 39dbfd420..af5f4007f 100644 --- a/passes/techmap/bmuxmap.cc +++ b/passes/techmap/bmuxmap.cc @@ -87,33 +87,34 @@ struct BmuxmapPass : public Pass { { int num_cases = 1 << s_width; SigSpec new_a = SigSpec(State::Sx, width); - SigSpec new_s = module->addWire(NEW_ID, num_cases); - SigSpec new_data = module->addWire(NEW_ID, width); - for (int val = 0; val < num_cases; val++) - { - module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]); + SigSpec new_s = module->addWire(NEW_ID2_SUFFIX("sel"), num_cases); // SILIMATE: Improve the naming + SigSpec new_data = module->addWire(NEW_ID2_SUFFIX("data"), width); // SILIMATE: Improve the naming + for (int val = 0; val < num_cases; val++) { + RTLIL::Cell *eq = module->addEq(NEW_ID2_SUFFIX("eq"), sel, SigSpec(val, GetSize(sel)), new_s[val]); // SILIMATE: Improve the naming + for (auto attr : cell->attributes) // SILIMATE: Copy all attributes from original cell to new cell + eq->attributes[attr.first] = attr.second; } - IdString new_id = IdString("$" + cell->name.str()); - // SILIMATE: Use uniquified ID with $ - // TODO: improve this - while (module->count_id(new_id) > 0) new_id = IdString("$" + new_id.str()); - RTLIL::Cell *pmux = module->addPmux(new_id, new_a, data, new_s, new_data); - pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - pmux->set_bool_attribute(IdString("\\bmuxmap")); + IdString cell_name = cell->name; // SILIMATE: Save the original cell name + module->rename(cell_name, NEW_ID); // SILIMATE: Rename the original cell, which will be deleted + RTLIL::Cell *pmux = module->addPmux(cell_name, new_a, data, new_s, new_data); // SILIMATE: Improve the naming + for (auto attr : cell->attributes) // SILIMATE: Copy all attributes from original cell to new cell + pmux->attributes[attr.first] = attr.second; + pmux->set_bool_attribute("\\bmuxmap"); // SILIMATE: Mark the cell as created by bmuxmap data = new_data; } else { for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); + SigSpec new_data = module->addWire(NEW_ID2_SUFFIX("data"), GetSize(data)/2); // SILIMATE: Improve the naming for (int i = 0; i < GetSize(new_data); i += width) { - RTLIL::Cell *mux = module->addMux(NEW_ID, + RTLIL::Cell *mux = module->addMux(NEW_ID2, // SILIMATE: Improve the naming data.extract(i*2, width), data.extract(i*2+width, width), sel[idx], new_data.extract(i, width)); - mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - mux->set_bool_attribute(IdString("\\bmuxmap")); + for (auto attr : cell->attributes) // SILIMATE: Copy all attributes from original cell to new cell + mux->attributes[attr.first] = attr.second; + mux->set_bool_attribute("\\bmuxmap"); // SILIMATE: Mark the cell as created by bmuxmap } data = new_data; } diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 892e9a364..20ff94bf7 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -270,11 +270,11 @@ struct ExtractReducePass : public Pass } if (head_cell->type == ID($_AND_)) { - module->addReduceAnd(NEW_ID, input, output); + module->addReduceAnd(NEW_ID2_SUFFIX("reduce_and"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming } else if (head_cell->type == ID($_OR_)) { - module->addReduceOr(NEW_ID, input, output); + module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming } else if (head_cell->type == ID($_XOR_)) { - module->addReduceXor(NEW_ID, input, output); + module->addReduceXor(NEW_ID2_SUFFIX("reduce_xor"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming } else { log_assert(false); } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 7461460fe..e272b6a4a 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -35,7 +35,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_NOT_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); @@ -72,7 +72,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEW_ID2, gate_type); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); @@ -114,7 +114,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) while (sig_a.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID2_SUFFIX("sig_t"), sig_a.size() / 2); // SILIMATE: Improve the naming for (int i = 0; i < sig_a.size(); i += 2) { @@ -123,7 +123,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) continue; } - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEW_ID2, gate_type); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); @@ -135,8 +135,8 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } if (cell->type == ID($reduce_xnor)) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID); - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID2_SUFFIX("sig_t")); // SILIMATE: Improve the naming + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_NOT_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); @@ -155,7 +155,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell { while (sig.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID2_SUFFIX("sig_t"), sig.size() / 2); // SILIMATE: Improve the naming for (int i = 0; i < sig.size(); i += 2) { @@ -164,7 +164,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell continue; } - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_OR_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig[i]); gate->setPort(ID::B, sig[i+1]); @@ -193,7 +193,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) sig_y = sig_y.extract(0, 1); } - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_NOT_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); @@ -222,7 +222,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($logic_or)) gate_type = ID($_OR_); log_assert(!gate_type.empty()); - RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); + RTLIL::Cell *gate = module->addCell(NEW_ID2, gate_type); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); @@ -237,20 +237,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); bool is_ne = cell->type.in(ID($ne), ID($nex)); - RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); - RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); + RTLIL::SigSpec xor_out = module->addWire(NEW_ID2_SUFFIX("xor_out"), max(GetSize(sig_a), GetSize(sig_b))); // SILIMATE: Improve the naming + RTLIL::Cell *xor_cell = module->addXor(NEW_ID2, sig_a, sig_b, xor_out, is_signed, cell->get_src_attribute()); // SILIMATE: Improve the naming xor_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_bitop(module, xor_cell); module->remove(xor_cell); - RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); - RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); + RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID2_SUFFIX("reduce_out")); // SILIMATE: Improve the naming + RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), xor_out, reduce_out, false, cell->get_src_attribute()); // SILIMATE: Improve the naming reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { - RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); + RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID2_SUFFIX("not"), reduce_out, sig_y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming not_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_lognot(module, not_cell); module->remove(not_cell); @@ -264,7 +264,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->getPort(ID::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); @@ -281,7 +281,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->getPort(ID::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); @@ -297,7 +297,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->getPort(ID::Y); for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_TBUF_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::E, sig_e); @@ -312,10 +312,10 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) int width = GetSize(cell->getPort(ID::Y)); for (int idx = 0; idx < GetSize(sel); idx++) { - SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2); + SigSpec new_data = module->addWire(NEW_ID2_SUFFIX("data"), GetSize(data)/2); // SILIMATE: Improve the naming for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, data[i*2+k]); gate->setPort(ID::B, data[i*2+width+k]); @@ -336,9 +336,9 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int()); for (int idx = 0; GetSize(lut_data) > 1; idx++) { - SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); + SigSpec new_lut_data = module->addWire(NEW_ID2_SUFFIX("data"), GetSize(lut_data)/2); // SILIMATE: Improve the naming for (int i = 0; i < GetSize(lut_data); i += 2) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, lut_data[i]); gate->setPort(ID::B, lut_data[i+1]); @@ -375,10 +375,10 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) } } - products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1); + products.append(GetSize(in) > 0 ? module->Eq(NEW_ID2_SUFFIX("eq"), in, pat, false, cell->get_src_attribute()) : State::S1); // SILIMATE: Improve the naming } - module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products)); + module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID2_SUFFIX("reduce_or"), products, false, cell->get_src_attribute())); // SILIMATE: Improve the naming } void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)