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Improve naming: big fix

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This commit is contained in:
Akash Levy 2024-11-11 17:06:11 -08:00
parent ea76abdaee
commit 894c9816d3
18 changed files with 205 additions and 155 deletions
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3
passes/opt/muxpack.cc
View file

@ -276,6 +276,7 @@ struct MuxpackWorker
for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i];
Cell* cell = cursor_cell; // SILIMATE: Set cell to cursor cell for better naming
if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
b_sig.append(cursor_cell->getPort(ID::B));
s_sig.append(cursor_cell->getPort(ID::S));
@ -283,7 +284,7 @@ struct MuxpackWorker
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
s_sig.append(module->LogicNot(NEW_ID2_SUFFIX("sel"), cursor_cell->getPort(ID::S), false, cell->get_src_attribute())); // SILIMATE: Improve the naming
}
remove_cells.insert(cursor_cell);
}

3
passes/opt/opt_balance_tree.cc
View file

@ -207,6 +207,7 @@ struct OptBalanceTreeWorker {
// Get mid, midnext (at index mid+1) and end of chain
Cell *mid_cell = chain[GetSize(chain) / 2];
Cell *cell = mid_cell; // SILIMATE: Set cell to mid_cell for better naming
Cell *midnext_cell = chain[GetSize(chain) / 2 + 1];
Cell *end_cell = chain.back();
log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n",
@ -227,7 +228,7 @@ struct OptBalanceTreeWorker {
SigSpec end_y_sig = sigmap(end_cell->getPort(ID::Y));
// Create new mid wire
Wire *mid_wire = module->addWire(NEW_ID, GetSize(end_y_sig));
Wire *mid_wire = module->addWire(NEW_ID2_SUFFIX("mid"), GetSize(end_y_sig)); // SILIMATE: Improve the naming
// Perform rotation
mid_cell->setPort(mid_non_chain_port, mid_wire);

72
passes/opt/opt_dff.cc
View file

@ -175,7 +175,7 @@ struct OptDffWorker
// TBD
}
ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates)
ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates, Module *module, Cell *cell)
{
if (patterns.empty() && GetSize(ctrls) == 1) {
return *ctrls.begin();
@ -191,8 +191,8 @@ struct OptDffWorker
s2.append(it.second);
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);
RTLIL::SigSpec y = module->addWire(NEW_ID2_SUFFIX("pat_y")); // SILIMATE: Improve the naming
RTLIL::Cell *c = module->addNe(NEW_ID2_SUFFIX("pat_ne"), s1, s2, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (make_gates) {
simplemap(module, c);
@ -205,9 +205,9 @@ struct OptDffWorker
if (item.second)
or_input.append(item.first);
else if (make_gates)
or_input.append(module->NotGate(NEW_ID, item.first));
or_input.append(module->NotGate(NEW_ID2_SUFFIX("ctrl_inv"), item.first, cell->get_src_attribute())); // SILIMATE: Improve the naming
else
or_input.append(module->Not(NEW_ID, item.first));
or_input.append(module->Not(NEW_ID2_SUFFIX("ctrl_inv"), item.first, false, cell->get_src_attribute())); // SILIMATE: Improve the naming
}
if (GetSize(or_input) == 0)
@ -216,8 +216,8 @@ struct OptDffWorker
if (GetSize(or_input) == 1)
return ctrl_t(or_input, true);
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEW_ID2_SUFFIX("pat_logic_y")); // SILIMATE: Improve the naming
RTLIL::Cell *c = module->addReduceAnd(NEW_ID2_SUFFIX("pat_logic_reduce_and"), or_input, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (make_gates) {
simplemap(module, c);
@ -227,7 +227,7 @@ struct OptDffWorker
return ctrl_t(y, true);
}
ctrl_t combine_resets(const ctrls_t &ctrls, bool make_gates)
ctrl_t combine_resets(const ctrls_t &ctrls, bool make_gates, Module *module, Cell *cell)
{
if (GetSize(ctrls) == 1) {
return *ctrls.begin();
@ -245,13 +245,17 @@ struct OptDffWorker
if (item.second == final_pol)
or_input.append(item.first);
else if (make_gates)
or_input.append(module->NotGate(NEW_ID, item.first));
or_input.append(module->NotGate(NEW_ID2_SUFFIX("comb_rst_inv"), item.first, cell->get_src_attribute())); // SILIMATE: Improve the naming
else
or_input.append(module->Not(NEW_ID, item.first));
or_input.append(module->Not(NEW_ID2_SUFFIX("comb_rst_inv"), item.first, false, cell->get_src_attribute())); // SILIMATE: Improve the naming
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEW_ID2_SUFFIX("comb_rst_y")); // SILIMATE: Improve the naming
RTLIL::Cell *c;
if (final_pol)
c = module->addReduceOr(NEW_ID2_SUFFIX("comb_rst_reduce_or"), or_input, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
c = module->addReduceAnd(NEW_ID2_SUFFIX("comb_rst_reduce_and"), or_input, y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (make_gates) {
simplemap(module, c);
@ -295,9 +299,9 @@ struct OptDffWorker
if (!ff.pol_clr) {
module->connect(ff.sig_q[i], ff.sig_clr[i]);
} else if (ff.is_fine) {
module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNotGate(NEW_ID2_SUFFIX("aactive_set"), ff.sig_clr[i], ff.sig_q[i], cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNot(NEW_ID2_SUFFIX("aactive_set"), ff.sig_clr[i], ff.sig_q[i], false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
@ -396,34 +400,34 @@ struct OptDffWorker
SigSpec tmp;
if (ff.is_fine) {
if (ff.pol_set)
tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set);
tmp = module->MuxGate(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, State::S1, ff.sig_set, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);
tmp = module->MuxGate(NEW_ID2_SUFFIX("aactive_aload"), State::S1, ff.sig_ad, ff.sig_set, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (ff.pol_clr)
module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), tmp, State::S0, ff.sig_clr, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), State::S0, tmp, ff.sig_clr, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
if (ff.pol_set)
tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set);
tmp = module->Or(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, ff.sig_set, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));
tmp = module->Or(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, module->Not(NEW_ID2_SUFFIX("aactive_aload_inv"), ff.sig_set, false, cell->get_src_attribute())); // SILIMATE: Improve the naming
if (ff.pol_clr)
module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
module->addAnd(NEW_ID2_SUFFIX("aactive_aload"), tmp, module->Not(NEW_ID2_SUFFIX("aactive_aload_inv"), ff.sig_clr, false, cell->get_src_attribute()), ff.sig_q); // SILIMATE: Improve the naming
else
module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
module->addAnd(NEW_ID2_SUFFIX("aactive_aload"), tmp, ff.sig_clr, ff.sig_q, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else if (ff.has_arst) {
if (ff.is_fine) {
if (ff.pol_arst)
module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q);
module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q);
module->addMuxGate(NEW_ID2_SUFFIX("aactive_aload"), ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
if (ff.pol_arst)
module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q);
module->addMux(NEW_ID2_SUFFIX("aactive_aload"), ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q);
module->addMux(NEW_ID2_SUFFIX("aactive_aload"), ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
} else {
module->connect(ff.sig_q, ff.sig_ad);
@ -539,20 +543,20 @@ struct OptDffWorker
if (ff.has_ce && ff.ce_over_srst) {
if (!ff.pol_ce) {
if (ff.is_fine)
ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce);
ff.sig_ce = module->NotGate(NEW_ID2_SUFFIX("ce"), ff.sig_ce, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
ff.sig_ce = module->Not(NEW_ID, ff.sig_ce);
ff.sig_ce = module->Not(NEW_ID2_SUFFIX("ce"), ff.sig_ce, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
if (!ff.pol_srst) {
if (ff.is_fine)
ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst);
ff.sig_srst = module->NotGate(NEW_ID2_SUFFIX("srst"), ff.sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
ff.sig_srst = module->Not(NEW_ID, ff.sig_srst);
ff.sig_srst = module->Not(NEW_ID2_SUFFIX("srst"), ff.sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
if (ff.is_fine)
ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst);
ff.sig_ce = module->AndGate(NEW_ID2_SUFFIX("ce"), ff.sig_ce, ff.sig_srst, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst);
ff.sig_ce = module->And(NEW_ID2_SUFFIX("ce"), ff.sig_ce, ff.sig_srst, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
ff.pol_ce = true;
} else {
ff.pol_ce = ff.pol_srst;
@ -636,7 +640,7 @@ struct OptDffWorker
int j = it.second[i];
new_ff.val_srst.bits().push_back(val_srst[j]);
}
ctrl_t srst = combine_resets(it.first, ff.is_fine);
ctrl_t srst = combine_resets(it.first, ff.is_fine, module, cell);
new_ff.has_srst = true;
new_ff.sig_srst = srst.first;
@ -700,7 +704,7 @@ struct OptDffWorker
for (auto &it : groups) {
FfData new_ff = ff.slice(it.second);
ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine);
ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine, module, cell);
new_ff.has_ce = true;
new_ff.sig_ce = en.first;

94
passes/opt/opt_expr.cc
View file

@ -202,7 +202,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
if (grouped_bits[i].empty())
continue;
RTLIL::SigSpec new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_y = module->addWire(NEW_ID2_SUFFIX("grp_y"), GetSize(grouped_bits[i])); // SILIMATE: Improve the naming
RTLIL::SigSpec new_a, new_b;
RTLIL::SigSig new_conn;
@ -247,9 +247,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
else if (new_a[i] == State::S0 || new_a[i] == State::S1) {
undef_a.append(new_a[i]);
if (cell->type == ID($xor))
undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]);
undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID2_SUFFIX("grp_undef_b"), new_b[i], false, cell->get_src_attribute()).as_bit() : new_b[i]); // SILIMATE: Improve the naming
else if (cell->type == ID($xnor))
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit());
undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID2_SUFFIX("grp_undef_b"), new_b[i], false, cell->get_src_attribute()).as_bit()); // SILIMATE: Improve the naming
else log_abort();
undef_y.append(new_y[i]);
}
@ -272,8 +272,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_y = std::move(def_y);
}
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
// SILIMATE: New cell takes on old cell's name
RTLIL::IdString cell_name = cell->name;
module->rename(cell->name, NEW_ID);
RTLIL::Cell *c = module->addCell(cell_name, cell->type);
c->set_src_attribute(cell->get_src_attribute());
c->setPort(ID::A, new_a);
c->parameters[ID::A_WIDTH] = new_a.size();
@ -612,9 +615,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xor_buffer");
SigSpec sig_y;
if (cell->type == ID($xor))
sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
sig_y = (sig_b == State::S1 ? module->Not(NEW_ID2_SUFFIX("xor_inv"), sig_a, false, cell->get_src_attribute()).as_bit() : sig_a); // SILIMATE: Improve the naming
else if (cell->type == ID($_XOR_))
sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID2_SUFFIX("xor_inv"), sig_a, cell->get_src_attribute()) : sig_a); // SILIMATE: Improve the naming
else log_abort();
replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
goto next_cell;
@ -623,12 +626,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.xnor_buffer");
SigSpec sig_y;
if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID2_SUFFIX("xnor_inv"), sig_a, false, cell->get_src_attribute()).as_bit()); // SILIMATE: Improve the naming
int width = cell->getParam(ID::Y_WIDTH).as_int();
sig_y.append(RTLIL::Const(State::S1, width-1));
}
else if (cell->type == ID($_XNOR_))
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID2_SUFFIX("xnor_inv"), sig_a, cell->get_src_attribute())); // SILIMATE: Improve the naming
else log_abort();
replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
goto next_cell;
@ -693,12 +696,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1, y_new_x;
// SILIMATE: New cell takes on old cell's name
RTLIL::IdString cell_name = cell->name;
module->rename(cell->name, NEW_ID);
if (cell->type == ID($and)) {
if (!y_group_0.empty()) y_new_0 = Const(State::S0, GetSize(y_group_0));
if (!y_group_1.empty()) y_new_1 = b_group_1;
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->And(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->And(cell_name, Const(State::Sx, GetSize(y_group_x)), b_group_x, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
y_new_x = Const(State::S0, GetSize(y_group_x));
}
@ -707,16 +714,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!y_group_1.empty()) y_new_1 = Const(State::S1, GetSize(y_group_1));
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Or(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Or(cell_name, Const(State::Sx, GetSize(y_group_x)), b_group_x, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
y_new_x = Const(State::S1, GetSize(y_group_x));
}
} else if (cell->type.in(ID($xor), ID($xnor))) {
if (!y_group_0.empty()) y_new_0 = b_group_0;
if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID, b_group_1);
if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID2_SUFFIX2("inv"), b_group_1, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (!y_group_x.empty()) {
if (keepdc)
y_new_x = module->Xor(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
y_new_x = module->Xor(cell_name, Const(State::Sx, GetSize(y_group_x)), b_group_x, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
y_new_x = Const(State::Sx, GetSize(y_group_x));
}
@ -762,6 +769,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
else if (sig_a.is_fully_def() || sig_b.is_fully_def())
{
// SILIMATE: New cell takes on old cell's name
RTLIL::IdString cell_name = cell->name;
module->rename(cell->name, NEW_ID);
bool flip = !sig_a.is_fully_def();
if (flip)
std::swap(sig_a, sig_b);
@ -779,11 +790,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1;
if (flip) {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, module->Not(NEW_ID, s_group_0));
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, s_group_1);
if (!y_group_0.empty()) y_new_0 = module->And(cell_name, b_group_0, module->Not(NEW_ID2_SUFFIX2("inv"), s_group_0, false, cell->get_src_attribute()), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (!y_group_1.empty()) y_new_1 = module->Or(cell_name, b_group_1, s_group_1, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
} else {
if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, s_group_0);
if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, module->Not(NEW_ID, s_group_1));
if (!y_group_0.empty()) y_new_0 = module->And(cell_name, b_group_0, s_group_0, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
if (!y_group_1.empty()) y_new_1 = module->Or(cell_name, b_group_1, module->Not(NEW_ID2_SUFFIX2("inv"), s_group_1, false, cell->get_src_attribute()), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
module->connect(y_group_0, y_new_0);
@ -996,12 +1007,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigBit a = sig_a[i];
if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID2_SUFFIX("sig_x_inv"), a, false, cell->get_src_attribute()).as_bit() : a); // SILIMATE: Improve the naming
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_y[i], bi ? module->Not(NEW_ID2_SUFFIX("sig_y_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID2_SUFFIX("sig_x_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else
@ -1418,7 +1429,7 @@ skip_fine_alu:
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(ID::A);
a.extend_u0(y_width, is_signed);
module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a));
module->connect(cell->getPort(ID::X), module->Not(NEW_ID2_SUFFIX("sig_ci_inv"), a, false, cell->get_src_attribute())); // SILIMATE: Improve the naming
module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width));
} else {
/* add */
@ -1834,13 +1845,13 @@ skip_identity:
// Truncating division is the same as flooring division, except when
// the result is negative and there is a remainder - then trunc = floor + 1
if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {
Wire *flooring = module->addWire(NEW_ID, sig_y.size());
Wire *flooring = module->addWire(NEW_ID2_SUFFIX("flooring"), sig_y.size()); // SILIMATE: Improve the naming
cell->setPort(ID::Y, flooring);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);
module->addAdd(NEW_ID, flooring, should_add, sig_y);
SigSpec rem_nonzero = module->ReduceOr(NEW_ID2_SUFFIX("rem_nonzero"), sig_a.extract(0, exp)); // SILIMATE: Improve the naming
SigSpec should_add = module->And(NEW_ID2_SUFFIX("should_add"), a_sign, rem_nonzero); // SILIMATE: Improve the naming
module->addAdd(NEW_ID2_SUFFIX("add"), flooring, should_add, sig_y); // SILIMATE: Improve the naming
}
cell->check();
@ -1862,11 +1873,11 @@ skip_identity:
SigSpec truncating = sig_a.extract(0, exp);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec extend_bit = module->And(NEW_ID, a_sign, rem_nonzero);
SigSpec rem_nonzero = module->ReduceOr(NEW_ID2_SUFFIX("rem_nonzero"), sig_a.extract(0, exp), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
SigSpec extend_bit = module->And(NEW_ID2_SUFFIX("extend_bit"), a_sign, rem_nonzero, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
truncating.append(extend_bit);
module->addPos(NEW_ID, truncating, sig_y, true);
module->addPos(NEW_ID2_SUFFIX("pos"), truncating, sig_y, true, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
else
{
@ -1949,7 +1960,12 @@ skip_identity:
int sz = cur - prev;
bool last = cur == GetSize(sig_y);
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
// SILIMATE: New cell takes on old cell's name
RTLIL::IdString cell_name = cell->name;
module->rename(cell->name, NEW_ID);
RTLIL::Cell *c = module->addCell(cell_name, cell->type); // SILIMATE: Improve the naming
c->set_src_attribute(cell->get_src_attribute());
c->setPort(ID::A, sig_a.extract(prev, sz));
c->setPort(ID::B, sig_b.extract(prev, sz));
c->setPort(ID::BI, sig_bi);
@ -1959,7 +1975,7 @@ skip_identity:
RTLIL::SigSpec new_co = sig_co.extract(prev, sz);
if (p.second != State::Sx) {
module->connect(new_co[sz-1], p.second);
RTLIL::Wire *dummy = module->addWire(NEW_ID);
RTLIL::Wire *dummy = module->addWire(NEW_ID2_SUFFIX2("dummy")); // SILIMATE: Improve the naming
new_co[sz-1] = dummy;
}
c->setPort(ID::CO, new_co);
@ -2124,16 +2140,24 @@ skip_alu_split:
if (cmp_type == ID($lt))
{
// SILIMATE: New cell takes on old cell's name
RTLIL::IdString cell_name = cell->name;
module->rename(cell->name, NEW_ID);
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
module->addLogicNot(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addLogicNot(cell_name, var_high_sig, cell->getPort(ID::Y), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
remove = true;
}
if (cmp_type == ID($ge))
{
// SILIMATE: New cell takes on old cell's name
RTLIL::IdString cell_name = cell->name;
module->rename(cell->name, NEW_ID);
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
module->addReduceOr(NEW_ID, var_high_sig, cell->getPort(ID::Y));
module->addReduceOr(cell_name, var_high_sig, cell->getPort(ID::Y), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
remove = true;
}
}
@ -2173,9 +2197,13 @@ skip_alu_split:
}
if (const_sig.is_fully_zero() && cmp_type == ID($ge))
{
// SILIMATE: New cell takes on old cell's name
RTLIL::IdString cell_name = cell->name;
module->rename(cell->name, NEW_ID);
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y));
module->addLogicNot(cell_name, var_sig[var_width - 1], cell->getPort(ID::Y), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
remove = true;
}
}

2
passes/opt/opt_mem.cc
View file

@ -125,7 +125,7 @@ struct OptMemPass : public Pass {
module->connect(port.data[bidx], bit);
} else {
// The FF will most likely be redundant, but it's up to opt_dff to deal with this.
FfData ff(module, &initvals, NEW_ID);
FfData ff(module, &initvals, NEW_MEM_ID_SUFFIX("ffdata")); // SILIMATE: Improve the naming
ff.width = 1;
ff.has_clk = true;
ff.sig_clk = port.clk;

8
passes/opt/opt_mem_feedback.cc
View file

@ -106,7 +106,7 @@ struct OptMemFeedbackWorker
find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, wrport_idx, data_bit_idx, paths);
}
RTLIL::SigBit conditions_to_logic(pool<dict<RTLIL::SigBit, bool>> &conditions, SigBit olden)
RTLIL::SigBit conditions_to_logic(pool<dict<RTLIL::SigBit, bool>> &conditions, SigBit olden, Module *module, Mem &mem)
{
auto key = make_pair(conditions, olden);
@ -120,7 +120,7 @@ struct OptMemFeedbackWorker
sig1.append(it.first);
sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
}
terms.append(module->Ne(NEW_ID, sig1, sig2));
terms.append(module->Ne(NEW_MEM_ID_SUFFIX("cond_ne"), sig1, sig2, false, mem.get_src_attribute())); // SILIMATE: Improve the naming
}
if (olden != State::S1)
@ -130,7 +130,7 @@ struct OptMemFeedbackWorker
terms = State::S1;
if (GetSize(terms) > 1)
terms = module->ReduceAnd(NEW_ID, terms);
terms = module->ReduceAnd(NEW_MEM_ID_SUFFIX("cond_reduce_and"), terms, false, mem.get_src_attribute()); // SILIMATE: Improve the naming
return conditions_logic_cache[key] = terms;
}
@ -255,7 +255,7 @@ struct OptMemFeedbackWorker
int bit = it.first.second;
auto &port = mem.wr_ports[wrport_idx];
port.en[bit] = conditions_to_logic(it.second, port.en[bit]);
port.en[bit] = conditions_to_logic(it.second, port.en[bit], module, mem);
log(" Port %d bit %d: added enable logic for %d different cases.\n", wrport_idx, bit, GetSize(it.second));
}