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Improve naming: big fix

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This commit is contained in:
Akash Levy 2024-11-11 17:06:11 -08:00
parent ea76abdaee
commit 894c9816d3
18 changed files with 205 additions and 155 deletions
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13
passes/memory/memory_map.cc
View file

@ -82,19 +82,18 @@ struct MemoryMapWorker
return sstr.str();
}
RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val)
RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val, Module *module, Mem &mem)
{
std::pair<RTLIL::SigSpec, RTLIL::SigSpec> key(addr_sig, addr_val);
log_assert(GetSize(addr_sig) == GetSize(addr_val));
if (decoder_cache.count(key) == 0) {
if (GetSize(addr_sig) < 2) {
decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val);
decoder_cache[key] = module->Eq(NEW_MEM_ID_SUFFIX("addr_decode"), addr_sig, addr_val, false, mem.get_src_attribute()); // SILIMATE: Improve the naming
} else {
int split_at = GetSize(addr_sig) / 2;
RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at));
RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at));
decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq);
RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at), module, mem);
RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at), module, mem);
decoder_cache[key] = module->And(NEW_MEM_ID_SUFFIX("addr_decode"), left_eq, right_eq, false, mem.get_src_attribute()); // SILIMATE: Improve the naming
}
}
@ -329,7 +328,7 @@ struct MemoryMapWorker
{
auto &port = mem.wr_ports[j];
RTLIL::SigSpec wr_addr = port.addr.extract_end(port.wide_log2);
RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(addr >> port.wide_log2, GetSize(wr_addr)));
RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(addr >> port.wide_log2, GetSize(wr_addr)), module, mem);
int sub = addr & ((1 << port.wide_log2) - 1);

16
passes/memory/memory_share.cc
View file

@ -163,7 +163,7 @@ struct MemoryShareWorker
port2.addr = addr2;
mem.prepare_rd_merge(i, j, &initvals);
mem.widen_prep(wide_log2);
SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2);
SigSpec new_data = module->addWire(NEW_MEM_ID_SUFFIX("data"), mem.width << wide_log2); // SILIMATE: Improve the naming
module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2));
module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2));
for (int k = 0; k < wide_log2; k++)
@ -270,8 +270,8 @@ struct MemoryShareWorker
port1.data.replace(pos, port2.data.extract(pos, width));
new_en = port2.en[pos];
} else {
port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos]));
new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]);
port1.data.replace(pos, module->Mux(NEW_MEM_ID_SUFFIX("data_mux"), port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos], mem.get_src_attribute())); // SILIMATE: Improve the naming
new_en = module->Or(NEW_MEM_ID_SUFFIX("en"), port1.en[pos], port2.en[pos], false, mem.get_src_attribute()); // SILIMATE: Improve the naming
}
for (int k = pos; k < epos; k++)
port1.en[k] = new_en;
@ -423,21 +423,21 @@ struct MemoryShareWorker
RTLIL::SigSpec this_data = port2.data;
std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(port2.en);
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_MEM_ID_SUFFIX("en_active"), this_en, false, mem.get_src_attribute()); // SILIMATE: Improve the naming
if (GetSize(last_addr) < GetSize(this_addr))
last_addr.extend_u0(GetSize(this_addr));
else
this_addr.extend_u0(GetSize(last_addr));
SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active);
SigSpec new_addr = module->Mux(NEW_MEM_ID_SUFFIX("addr"), last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active, mem.get_src_attribute()); // SILIMATE: Improve the naming
port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)});
port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
port1.data = module->Mux(NEW_MEM_ID_SUFFIX("data"), last_data, this_data, this_en_active, mem.get_src_attribute()); // SILIMATE: Improve the naming
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
RTLIL::Wire *grouped_en = module->addWire(NEW_MEM_ID_SUFFIX("grouped_en"), 0); // SILIMATE: Improve the naming
for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
@ -450,7 +450,7 @@ struct MemoryShareWorker
en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
}
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
module->addMux(NEW_MEM_ID_SUFFIX("en_mux"), grouped_last_en, grouped_this_en, this_en_active, grouped_en, mem.get_src_attribute()); // SILIMATE: Improve the naming
port1.en = en;
port2.removed = true;