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verilog: fix string literal regular expression (#5187)

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* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
This commit is contained in:
garytwong 2025-06-19 16:41:18 +00:00 • committed by GitHub
parent cd71f190cd
commit 834a7294b7
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2 changed files with 6 additions and 1 deletions
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2
frontends/verilog/verilog_lexer.l
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@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s
} }
\" { BEGIN(STRING); } \" { BEGIN(STRING); }
<STRING>([^\"]|\\.)+ { yymore(); real_location = old_location; } <STRING>([^\\"]|\\.)+ { yymore(); real_location = old_location; }
<STRING>\" { <STRING>\" {
BEGIN(0); BEGIN(0);
char *yystr = strdup(yytext); char *yystr = strdup(yytext);

5
tests/verilog/bug5160.v Normal file
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@ -0,0 +1,5 @@
// Regression test for bug mentioned in #5160:
// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
module top;
initial $display( "\\" );
endmodule