diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 8148748d8..40162b8d3 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s
 }
 
 \"		{ BEGIN(STRING); }
-<STRING>([^\"]|\\.)+	{ yymore(); real_location = old_location; }
+<STRING>([^\\"]|\\.)+	{ yymore(); real_location = old_location; }
 <STRING>\"	{
 	BEGIN(0);
 	char *yystr = strdup(yytext);
diff --git a/tests/verilog/bug5160.v b/tests/verilog/bug5160.v
new file mode 100644
index 000000000..5b141a360
--- /dev/null
+++ b/tests/verilog/bug5160.v
@@ -0,0 +1,5 @@
+// Regression test for bug mentioned in #5160:
+// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
+module top;
+    initial $display( "\\" );
+endmodule