yosys/tests/verilog/bug5160.v at 834a7294b7c790612e9d1a686b374130b43d814e - mirrors/yosys - Libre-Chip.org

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garytwong 834a7294b7

verilog: fix string literal regular expression (#5187 )

* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).

2025-06-19 12:41:18 -04:00

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Verilog

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 // Regression test for bug mentioned in #5160:
 // https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
 module top;
     initial $display( "\\" );
 endmodule