mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-11 05:30:53 +00:00
Merge pull request #5265 from bhagwat-rahul/fix-package-import
Support package import
This commit is contained in:
commit
7f0e864d44
9 changed files with 119 additions and 0 deletions
14
tests/verilog/package_import_separate.sv
Normal file
14
tests/verilog/package_import_separate.sv
Normal file
|
@ -0,0 +1,14 @@
|
|||
package package_import_separate;
|
||||
|
||||
localparam integer
|
||||
DATAWIDTH = 8,
|
||||
ADDRWIDTH = 4;
|
||||
|
||||
localparam logic [2:0]
|
||||
IDLE = 3'b000,
|
||||
START = 3'b001,
|
||||
DATA = 3'b010,
|
||||
STOP = 3'b100,
|
||||
DONE = 3'b101;
|
||||
|
||||
endpackage
|
5
tests/verilog/package_import_separate.ys
Normal file
5
tests/verilog/package_import_separate.ys
Normal file
|
@ -0,0 +1,5 @@
|
|||
read_verilog -sv package_import_separate.sv
|
||||
read_verilog -sv package_import_separate_module.sv
|
||||
hierarchy -check
|
||||
proc
|
||||
opt -full
|
19
tests/verilog/package_import_separate_module.sv
Normal file
19
tests/verilog/package_import_separate_module.sv
Normal file
|
@ -0,0 +1,19 @@
|
|||
import package_import_separate::*;
|
||||
|
||||
module package_import_separate_module;
|
||||
logic [DATAWIDTH-1:0] data;
|
||||
logic [ADDRWIDTH-1:0] addr;
|
||||
logic [2:0] state;
|
||||
|
||||
always_comb begin
|
||||
case (state)
|
||||
IDLE: data = 8'h00;
|
||||
START: data = 8'h01;
|
||||
DATA: data = 8'h02;
|
||||
STOP: data = 8'h04;
|
||||
DONE: data = 8'h05;
|
||||
default: data = 8'hFF;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
Loading…
Add table
Add a link
Reference in a new issue