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19 lines
383 B
Systemverilog
19 lines
383 B
Systemverilog
import package_import_separate::*;
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module package_import_separate_module;
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logic [DATAWIDTH-1:0] data;
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logic [ADDRWIDTH-1:0] addr;
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logic [2:0] state;
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always_comb begin
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case (state)
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IDLE: data = 8'h00;
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START: data = 8'h01;
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DATA: data = 8'h02;
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STOP: data = 8'h04;
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DONE: data = 8'h05;
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default: data = 8'hFF;
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endcase
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end
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endmodule
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