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before some refactoring

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This commit is contained in:
Artur Swiderski 2020-10-31 00:59:48 +01:00
parent 42c5007cf6
commit 7a8efe9f1b
5 changed files with 16 additions and 150 deletions
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37
techlibs/intel_le/common/megafunction_bb.v
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@ -538,28 +538,6 @@ output eccstatus;
endmodule
(* blackbox *)
module cycloneiv_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1);
parameter logical_ram_name = "";
parameter logical_ram_depth = 32;
parameter logical_ram_width = 20;
parameter mixed_port_feed_through_mode = "new";
parameter first_bit_number = 0;
parameter first_address = 0;
parameter last_address = 31;
parameter address_width = 5;
parameter data_width = 1;
parameter byte_enable_mask_width = 1;
parameter port_b_data_out_clock = "NONE";
parameter [639:0] mem_init0 = 640'b0;
input [address_width-1:0] portaaddr, portbaddr;
input [data_width-1:0] portadatain;
output [data_width-1:0] portbdataout;
input ena0, clk0, clk1;
endmodule
(* blackbox *)
module cycloneiv_mac(ax, ay, resulta);
@ -577,21 +555,6 @@ output [result_a_width-1:0] resulta;
endmodule
(* blackbox *)
module cyclone10gx_mac(ax, ay, resulta);
parameter ax_width = 18;
parameter signed_max = "true";
parameter ay_scan_in_width = 18;
parameter signed_may = "true";
parameter result_a_width = 36;
parameter operation_mode = "M18X18_FULL";
input [ax_width-1:0] ax;
input [ay_scan_in_width-1:0] ay;
output [result_a_width-1:0] resulta;
endmodule
(* blackbox *)
module cycloneiv_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);