diff --git a/techlibs/intel_le/common/le_map.v b/techlibs/intel_le/common/le_map.v index 6697b2e78..a1881e17a 100644 --- a/techlibs/intel_le/common/le_map.v +++ b/techlibs/intel_le/common/le_map.v @@ -40,16 +40,6 @@ generate MISTRAL_ALUT4 #(.LUT(LUT)) _TECHMAP_REPLACE_( .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .Q(Y) ); - end else - if (WIDTH == 5) begin - MISTRAL_ALUT5 #(.LUT(LUT)) _TECHMAP_REPLACE_ ( - .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .Q(Y) - ); - end else - if (WIDTH == 6) begin - MISTRAL_ALUT6 #(.LUT(LUT)) _TECHMAP_REPLACE_ ( - .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .Q(Y) - ); end else begin wire _TECHMAP_FAIL_ = 1'b1; end diff --git a/techlibs/intel_le/common/le_sim.v b/techlibs/intel_le/common/le_sim.v index 465c7c14b..95d273c14 100644 --- a/techlibs/intel_le/common/le_sim.v +++ b/techlibs/intel_le/common/le_sim.v @@ -168,8 +168,6 @@ endspecify wire q0, q1; -//assign q0 = LUT >> sum_lutc_input == "cin" ? {'b0, CI, B, A}:{'b0, C, B, A}; -//assign q1 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A}; assign q0 = LUT >> {'b0, CI, B, A}; assign q1 = LUT >> {D, CI, B, A}; diff --git a/techlibs/intel_le/common/megafunction_bb.v b/techlibs/intel_le/common/megafunction_bb.v index 0f723f7a1..8eaaa62b8 100644 --- a/techlibs/intel_le/common/megafunction_bb.v +++ b/techlibs/intel_le/common/megafunction_bb.v @@ -538,28 +538,6 @@ output eccstatus; endmodule -(* blackbox *) -module cycloneiv_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1); - -parameter logical_ram_name = ""; -parameter logical_ram_depth = 32; -parameter logical_ram_width = 20; -parameter mixed_port_feed_through_mode = "new"; -parameter first_bit_number = 0; -parameter first_address = 0; -parameter last_address = 31; -parameter address_width = 5; -parameter data_width = 1; -parameter byte_enable_mask_width = 1; -parameter port_b_data_out_clock = "NONE"; -parameter [639:0] mem_init0 = 640'b0; - -input [address_width-1:0] portaaddr, portbaddr; -input [data_width-1:0] portadatain; -output [data_width-1:0] portbdataout; -input ena0, clk0, clk1; - -endmodule (* blackbox *) module cycloneiv_mac(ax, ay, resulta); @@ -577,21 +555,6 @@ output [result_a_width-1:0] resulta; endmodule -(* blackbox *) -module cyclone10gx_mac(ax, ay, resulta); - -parameter ax_width = 18; -parameter signed_max = "true"; -parameter ay_scan_in_width = 18; -parameter signed_may = "true"; -parameter result_a_width = 36; -parameter operation_mode = "M18X18_FULL"; - -input [ax_width-1:0] ax; -input [ay_scan_in_width-1:0] ay; -output [result_a_width-1:0] resulta; - -endmodule (* blackbox *) module cycloneiv_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0); diff --git a/techlibs/intel_le/common/mem_sim.v b/techlibs/intel_le/common/mem_sim.v index db5f40fb5..adc5c45cb 100644 --- a/techlibs/intel_le/common/mem_sim.v +++ b/techlibs/intel_le/common/mem_sim.v @@ -20,65 +20,14 @@ // a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and // 20 of them represent a physical MLAB. // -// How the MLAB works -// ------------------ -// MLABs are poorly documented, so the following information is based mainly -// on the simulation model and my knowledge of how memories like these work. -// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated -// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use -// `techmap` just for the sake of renaming the cell ports. -// -// The MLAB can be initialised to any value, but unfortunately Quartus only -// allows memory initialisation from a file. Since Yosys doesn't preserve input -// file information, or write the contents of an `initial` block to a file, -// Yosys can't currently initialise the MLAB in a way Quartus will accept. -// -// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN -// is high, writes it to the address in A1ADDR. A1EN can therefore be used to -// conditionally write data to the MLAB. -// -// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA, -// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed -// then the output can be fed to embedded flops. Presently, Yosys assumes -// Quartus will pack external flops into the MLAB, but this is an assumption -// that needs testing. -// The vendor sim model outputs 'x for a very short period (a few -// combinational delta cycles) after each write. This has been omitted from -// the following model because it's very difficult to trigger this in practice -// as clock cycles will be much longer than any potential blip of 'x, so the -// model can be treated as always returning a defined result. -(* abc9_box, lib_whitebox *) -module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA); - -reg [31:0] mem = 32'b0; - -// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V -specify - $setup(A1ADDR, posedge CLK1, 86); - $setup(A1DATA, posedge CLK1, 86); - $setup(A1EN, posedge CLK1, 86); - - (B1ADDR[0] => B1DATA) = 487; - (B1ADDR[1] => B1DATA) = 475; - (B1ADDR[2] => B1DATA) = 382; - (B1ADDR[3] => B1DATA) = 284; - (B1ADDR[4] => B1DATA) = 96; -endspecify - -always @(posedge CLK1) - if (A1EN) mem[A1ADDR] <= A1DATA; - -assign B1DATA = mem[B1ADDR]; - -endmodule // The M9K // -------- // TODO -module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); +module MISTRAL_M9K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 10; diff --git a/techlibs/intel_le/common/quartus_rename.v b/techlibs/intel_le/common/quartus_rename.v index 00449d522..39076206a 100644 --- a/techlibs/intel_le/common/quartus_rename.v +++ b/techlibs/intel_le/common/quartus_rename.v @@ -1,8 +1,12 @@ -`ifdef cycloneiv -`define LCELL cycloneiv_lcell_comb -`define MAC cycloneiv_mac -`define MLAB cycloneiv_mlab_cell +`ifdef cycloneiv + `define LCELL cycloneiv_lcell_comb + `define M9K cycloneiv_ram_block `endif +`ifdef cycloneive + `define LCELL cycloneive_lcell_comb + `define M9K cycloneive_ram_block +`endif + module __MISTRAL_VCC(output Q); @@ -53,62 +57,24 @@ endmodule module MISTRAL_NOT(input A, output Q); -NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q)); - +//NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q)); +assign Q = ~A; endmodule module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO); parameter LUT = 16'h0000; parameter sum_lutc_input = "datac"; -`LCELL #(.lut_mask({LUT}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .sumout(SO), .cout(CO)); +`LCELL #(.lut_mask({LUT}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .combout(SO), .cout(CO)); endmodule -module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA); - -parameter _TECHMAP_CELLNAME_ = ""; - -// Here we get to an unfortunate situation. The cell has a mem_init0 parameter, -// which takes in a hexadecimal string that could be used to initialise RAM. -// In the vendor simulation models, this appears to work fine, but Quartus, -// either intentionally or not, forgets about this parameter and initialises the -// RAM to zero. -// -// Because of this, RAM initialisation is presently disabled, but the source -// used to generate mem_init0 is kept (commented out) in case this gets fixed -// or an undocumented way to get Quartus to initialise from mem_init0 is found. - -`MLAB #( - .logical_ram_name(_TECHMAP_CELLNAME_), - .logical_ram_depth(32), - .logical_ram_width(1), - .mixed_port_feed_through_mode("Dont Care"), - .first_bit_number(0), - .first_address(0), - .last_address(31), - .address_width(5), - .data_width(1), - .byte_enable_mask_width(1), - .port_b_data_out_clock("NONE"), - // .mem_init0($sformatf("%08x", INIT)) -) _TECHMAP_REPLACE_ ( - .portaaddr(A1ADDR), - .portadatain(A1DATA), - .portbaddr(B1ADDR), - .portbdataout(B1DATA), - .ena0(A1EN), - .clk0(CLK1) -); - -endmodule - module MISTRAL_M9K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN); -parameter CFG_ABITS = 10; -parameter CFG_DBITS = 10; +parameter CFG_ABITS = 9; +parameter CFG_DBITS = 9; parameter _TECHMAP_CELLNAME_ = ""; @@ -117,10 +83,10 @@ input [CFG_DBITS-1:0] A1DATA; input CLK1, A1EN, B1EN; output [CFG_DBITS-1:0] B1DATA; -// Much like the MLAB, the M9K has mem_init[01234] parameters which would let +// The M9K has mem_init[01234] parameters which would let // you initialise the RAM cell via hex literals. If they were implemented. -cycloneiv_ram_block #( +`M9K #( .operation_mode("dual_port"), .logical_ram_name(_TECHMAP_CELLNAME_), .port_a_address_width(CFG_ABITS),