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https://github.com/YosysHQ/yosys
synced 2025-04-22 16:45:32 +00:00
some progress in le mapping
This commit is contained in:
Artur Swiderski
parent
53a95de62f
commit
42c5007cf6
4 changed files with 16 additions and 440 deletions
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@ -40,6 +40,7 @@ generate
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end else begin
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MISTRAL_ALUT_ARITH #(
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.LUT(16'b1010_1010_1010_1010), // Q = A
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.sum_lutc_input("cin")
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) le_start (
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.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
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.CI(1'b0),
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@ -54,7 +55,8 @@ genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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MISTRAL_ALUT_ARITH #(
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.LUT(16'b0110_0110_0110_0110) // Q = A ? ~B : B
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.LUT(16'b0110_0110_0110_0110), // Q = A ? ~B : B
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.sum_lutc_input("cin")
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) le_not_i (
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.A(BI), .B(BX[i]), .C(1'b0), .D(1'b0),
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.CI(1'b0),
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@ -63,13 +65,10 @@ generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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);
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MISTRAL_ALUT_ARITH #(
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.LUT(16'b1001_0110_1110_1000), // SUM = A xor B xor CI
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// CARRYi+1 = A and B or A and CI or B and CI
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//.sum_lutc_input("cin")
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.sum_lutc_input("cin")
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) le_i (
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.A(AA[i]), .B(BTOADDER[i]), .C(1'b1), .D(1'b1),
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.CI(LE_CARRY[i]),
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@ -77,65 +77,6 @@
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// SUMOUT 368 1342 1323 887 927 - 785 -
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// CARRYOUT 71 1082 1062 866 813 - 1198 -
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(* abc9_lut=2, lib_whitebox *)
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module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
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parameter [63:0] LUT = 64'h0000_0000_0000_0000;
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`ifdef cycloneiv
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specify
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(A => Q) = 605;
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(B => Q) = 583;
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(C => Q) = 510;
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(D => Q) = 512;
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(E => Q) = 400;
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(F => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 275;
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(B => Q) = 272;
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(C => Q) = 175;
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(D => Q) = 165;
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(E => Q) = 162;
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(F => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {F, E, D, C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
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parameter [31:0] LUT = 32'h0000_0000;
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`ifdef cycloneiv
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specify
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(A => Q) = 583;
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(B => Q) = 510;
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(C => Q) = 512;
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(D => Q) = 400;
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(E => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 272;
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(B => Q) = 175;
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(C => Q) = 165;
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(D => Q) = 162;
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(E => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {E, D, C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT4(input A, B, C, D, output Q);
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@ -150,14 +91,6 @@ specify
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(D => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 175;
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(B => Q) = 165;
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(C => Q) = 162;
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(D => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {D, C, B, A};
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@ -176,13 +109,6 @@ specify
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(C => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 165;
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(B => Q) = 162;
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(C => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {C, B, A};
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@ -200,12 +126,6 @@ specify
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(B => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 162;
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(B => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {B, A};
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@ -220,11 +140,6 @@ specify
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(A => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 53;
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endspecify
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`endif
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assign Q = ~A;
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@ -234,7 +149,7 @@ endmodule
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module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
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parameter LUT = 16'h0000;
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//parameter sum_lutc_input = "cin";
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parameter sum_lutc_input = "cin";
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`ifdef cycloneiv
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specify
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(A => SO) = 1342;
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@ -253,8 +168,8 @@ endspecify
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wire q0, q1;
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//assign q0 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A};
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//assign q1 = LUT >> sum_lutc_input == "cin" ? {'b0, CI, B, A}:{'b0, C, B, A};
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//assign q0 = LUT >> sum_lutc_input == "cin" ? {'b0, CI, B, A}:{'b0, C, B, A};
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//assign q1 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A};
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assign q0 = LUT >> {'b0, CI, B, A};
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assign q1 = LUT >> {D, CI, B, A};
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@ -266,281 +181,3 @@ assign CO = q0;
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endmodule
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/*
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// A, B, C0, C1, E0, E1, F0, F1: data inputs
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// CARRYIN: carry input
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// SHAREIN: shared-arithmetic input
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// CLK0, CLK1, CLK2: clock inputs
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//
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// COMB0, COMB1: combinational outputs
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// FF0, FF1, FF2, FF3: DFF outputs
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// SUM0, SUM1: adder outputs
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// CARRYOUT: carry output
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// SHAREOUT: shared-arithmetic output
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module MISTRAL_ALM(
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input A, B, C0, C1, E0, E1, F0, F1, CARRYIN, SHAREIN, // LUT path
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input CLK0, CLK1, CLK2, AC0, AC1, // FF path
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output COMB0, COMB1, SUM0, SUM1, CARRYOUT, SHAREOUT,
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output FF0, FF1, FF2, FF3
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);
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parameter LUT0 = 16'b0000;
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parameter LUT1 = 16'b0000;
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parameter LUT2 = 16'b0000;
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parameter LUT3 = 16'b0000;
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parameter INIT0 = 1'b0;
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parameter INIT1 = 1'b0;
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parameter INIT2 = 1'b0;
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parameter INIT3 = 1'b0;
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parameter C0_MUX = "C0";
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parameter C1_MUX = "C1";
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parameter F0_MUX = "VCC";
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parameter F1_MUX = "GND";
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parameter FEEDBACK0 = "FF0";
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parameter FEEDBACK1 = "FF2";
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parameter ADD_MUX = "LUT";
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parameter DFF01_DATA_MUX = "COMB";
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parameter DFF23_DATA_MUX = "COMB";
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parameter DFF0_CLK = "CLK0";
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parameter DFF1_CLK = "CLK0";
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parameter DFF2_CLK = "CLK0";
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parameter DFF3_CLK = "CLK0";
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parameter DFF0_AC = "AC0";
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parameter DFF1_AC = "AC0";
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parameter DFF2_AC = "AC0";
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parameter DFF3_AC = "AC0";
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// Feedback muxes from the flip-flop outputs.
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wire ff_feedback_mux0, ff_feedback_mux1;
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// C-input muxes which can be set to also use the F-input.
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wire c0_input_mux, c1_input_mux;
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// F-input muxes which can be set to a constant to allow LUT5 use.
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wire f0_input_mux, f1_input_mux;
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// Adder input muxes to select between shared-arithmetic mode and arithmetic mode.
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wire add0_input_mux, add1_input_mux;
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// Combinational-output muxes for LUT #1 and LUT #3
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wire lut1_comb_mux, lut3_comb_mux;
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// Sum-output muxes for LUT #1 and LUT #3
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wire lut1_sum_mux, lut3_sum_mux;
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// DFF data-input muxes
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wire dff01_data_mux, dff23_data_mux;
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// DFF clock selectors
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wire dff0_clk, dff1_clk, dff2_clk, dff3_clk;
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// DFF asynchronous-clear selectors
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wire dff0_ac, dff1_ac, dff2_ac, dff3_ac;
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// LUT, DFF and adder output wires for routing.
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wire lut0_out, lut1a_out, lut1b_out, lut2_out, lut3a_out, lut3b_out;
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wire dff0_out, dff1_out, dff2_out, dff3_out;
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wire add0_sum, add1_sum, add0_carry, add1_carry;
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generate
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if (FEEDBACK0 === "FF0")
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assign ff_feedback_mux0 = dff0_out;
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else if (FEEDBACK0 === "FF1")
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assign ff_feedback_mux0 = dff1_out;
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else
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$error("Invalid FEEDBACK0 setting!");
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if (FEEDBACK1 == "FF2")
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assign ff_feedback_mux1 = dff2_out;
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else if (FEEDBACK1 == "FF3")
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assign ff_feedback_mux1 = dff3_out;
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else
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$error("Invalid FEEDBACK1 setting!");
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if (C0_MUX === "C0")
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assign c0_input_mux = C0;
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else if (C0_MUX === "F1")
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assign c0_input_mux = F1;
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else if (C0_MUX === "FEEDBACK1")
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assign c0_input_mux = ff_feedback_mux1;
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else
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$error("Invalid C0_MUX setting!");
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if (C1_MUX === "C1")
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assign c1_input_mux = C1;
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else if (C1_MUX === "F0")
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assign c1_input_mux = F0;
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else if (C1_MUX === "FEEDBACK0")
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assign c1_input_mux = ff_feedback_mux0;
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else
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$error("Invalid C1_MUX setting!");
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// F0 == VCC is LUT5
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// F0 == F0 is LUT6
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// F0 == FEEDBACK is unknown
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if (F0_MUX === "VCC")
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assign f0_input_mux = 1'b1;
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else if (F0_MUX === "F0")
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assign f0_input_mux = F0;
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else if (F0_MUX === "FEEDBACK0")
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assign f0_input_mux = ff_feedback_mux0;
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else
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$error("Invalid F0_MUX setting!");
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// F1 == GND is LUT5
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// F1 == F1 is LUT6
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// F1 == FEEDBACK is unknown
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if (F1_MUX === "GND")
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assign f1_input_mux = 1'b0;
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else if (F1_MUX === "F1")
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assign f1_input_mux = F1;
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else if (F1_MUX === "FEEDBACK1")
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assign f1_input_mux = ff_feedback_mux1;
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else
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$error("Invalid F1_MUX setting!");
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if (ADD_MUX === "LUT") begin
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assign add0_input_mux = ~lut1_sum_mux;
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assign add1_input_mux = ~lut3_sum_mux;
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end else if (ADD_MUX === "SHARE") begin
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assign add0_input_mux = SHAREIN;
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assign add1_input_mux = lut1_comb_mux;
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end else
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$error("Invalid ADD_MUX setting!");
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if (DFF01_DATA_MUX === "COMB")
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assign dff01_data_mux = COMB0;
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else if (DFF01_DATA_MUX === "SUM")
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assign dff01_data_mux = SUM0;
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else
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$error("Invalid DFF01_DATA_MUX setting!");
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if (DFF23_DATA_MUX === "COMB")
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assign dff23_data_mux = COMB0;
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else if (DFF23_DATA_MUX === "SUM")
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assign dff23_data_mux = SUM0;
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else
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$error("Invalid DFF23_DATA_MUX setting!");
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if (DFF0_CLK === "CLK0")
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assign dff0_clk = CLK0;
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else if (DFF0_CLK === "CLK1")
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assign dff0_clk = CLK1;
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else if (DFF0_CLK === "CLK2")
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assign dff0_clk = CLK2;
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else
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$error("Invalid DFF0_CLK setting!");
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if (DFF1_CLK === "CLK0")
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assign dff1_clk = CLK0;
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else if (DFF1_CLK === "CLK1")
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assign dff1_clk = CLK1;
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else if (DFF1_CLK === "CLK2")
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assign dff1_clk = CLK2;
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else
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$error("Invalid DFF1_CLK setting!");
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if (DFF2_CLK === "CLK0")
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assign dff2_clk = CLK0;
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else if (DFF2_CLK === "CLK1")
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assign dff2_clk = CLK1;
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else if (DFF2_CLK === "CLK2")
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assign dff2_clk = CLK2;
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else
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$error("Invalid DFF2_CLK setting!");
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if (DFF3_CLK === "CLK0")
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assign dff3_clk = CLK0;
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else if (DFF3_CLK === "CLK1")
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assign dff3_clk = CLK1;
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else if (DFF3_CLK === "CLK2")
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assign dff3_clk = CLK2;
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else
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$error("Invalid DFF3_CLK setting!");
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if (DFF0_AC === "AC0")
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assign dff0_ac = AC0;
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else if (DFF0_AC === "AC1")
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assign dff0_ac = AC1;
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else
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$error("Invalid DFF0_AC setting!");
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if (DFF1_AC === "AC0")
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assign dff1_ac = AC0;
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else if (DFF1_AC === "AC1")
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assign dff1_ac = AC1;
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else
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$error("Invalid DFF1_AC setting!");
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if (DFF2_AC === "AC0")
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assign dff2_ac = AC0;
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else if (DFF2_AC === "AC1")
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assign dff2_ac = AC1;
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else
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$error("Invalid DFF2_AC setting!");
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if (DFF3_AC === "AC0")
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assign dff3_ac = AC0;
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else if (DFF3_AC === "AC1")
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assign dff3_ac = AC1;
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else
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$error("Invalid DFF3_AC setting!");
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endgenerate
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// F0 on the Quartus diagram
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MISTRAL_ALUT4 #(.LUT(LUT0)) lut0 (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut0_out));
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// F2 on the Quartus diagram
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MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_comb (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut1_comb_mux));
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MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_sum (.A(A), .B(B), .C(C0), .D(E0), .Q(lut1_sum_mux));
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// F1 on the Quartus diagram
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MISTRAL_ALUT4 #(.LUT(LUT2)) lut2 (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut2_out));
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// F3 on the Quartus diagram
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MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_comb (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut3_comb_mux));
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MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_sum (.A(A), .B(B), .C(C1), .D(E1), .Q(lut3_sum_mux));
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MISTRAL_FF #(.INIT(INIT0)) dff0 (.D(dff01_data_mux), .CLK(dff0_clk), .ACn(dff0_ac), .Q(dff0_out));
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MISTRAL_FF #(.INIT(INIT1)) dff1 (.D(dff01_data_mux), .CLK(dff1_clk), .ACn(dff1_ac), .Q(dff1_out));
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MISTRAL_FF #(.INIT(INIT2)) dff2 (.D(dff23_data_mux), .CLK(dff2_clk), .ACn(dff2_ac), .Q(dff2_out));
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MISTRAL_FF #(.INIT(INIT3)) dff3 (.D(dff23_data_mux), .CLK(dff3_clk), .ACn(dff3_ac), .Q(dff3_out));
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// Adders
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assign {add0_carry, add0_sum} = CARRYIN + lut0_out + lut1_sum_mux;
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assign {add1_carry, add1_sum} = add0_carry + lut2_out + lut3_sum_mux;
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||||
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// COMBOUT outputs on the Quartus diagram
|
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assign COMB0 = E0 ? (f0_input_mux ? lut3_comb_mux : lut1_comb_mux)
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: (f0_input_mux ? lut2_out : lut0_out);
|
||||
|
||||
assign COMB1 = E1 ? (f1_input_mux ? lut3_comb_mux : lut1_comb_mux)
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: (f1_input_mux ? lut2_out : lut0_out);
|
||||
|
||||
// SUMOUT output on the Quartus diagram
|
||||
assign SUM0 = add0_sum;
|
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assign SUM1 = add1_sum;
|
||||
|
||||
// COUT output on the Quartus diagram
|
||||
assign CARRYOUT = add1_carry;
|
||||
|
||||
// SHAREOUT output on the Quartus diagram
|
||||
assign SHAREOUT = lut3_comb_mux;
|
||||
|
||||
// REGOUT outputs on the Quartus diagram
|
||||
assign FF0 = dff0_out;
|
||||
assign FF1 = dff1_out;
|
||||
assign FF2 = dff2_out;
|
||||
assign FF3 = dff3_out;
|
||||
|
||||
endmodule
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
`ifdef cycloneiv
|
||||
`ifdef cycloneiv
|
||||
`define LCELL cycloneiv_lcell_comb
|
||||
`define MAC cycloneiv_mac
|
||||
`define MLAB cycloneiv_mlab_cell
|
||||
|
|
@ -29,24 +29,24 @@ endmodule
|
|||
|
||||
module MISTRAL_ALUT4(input A, B, C, D, output Q);
|
||||
parameter [15:0] LUT = 16'h0000;
|
||||
|
||||
`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
|
||||
parameter sum_lutc_input = "datac";
|
||||
`LCELL #(.lut_mask(LUT),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module MISTRAL_ALUT3(input A, B, C, output Q);
|
||||
parameter [7:0] LUT = 8'h00;
|
||||
|
||||
`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
|
||||
parameter sum_lutc_input = "datac";
|
||||
`LCELL #(.lut_mask({2{LUT}}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module MISTRAL_ALUT2(input A, B, output Q);
|
||||
parameter [3:0] LUT = 4'h0;
|
||||
|
||||
`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
|
||||
parameter sum_lutc_input = "datac";
|
||||
`LCELL #(.lut_mask({4{LUT}}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -60,8 +60,8 @@ endmodule
|
|||
|
||||
module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO);
|
||||
parameter LUT = 16'h0000;
|
||||
|
||||
`LCELL #(.lut_mask({16'h0, LUT})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .sumout(SO), .cout(CO));
|
||||
parameter sum_lutc_input = "datac";
|
||||
`LCELL #(.lut_mask({LUT}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .sumout(SO), .cout(CO));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -48,67 +48,7 @@ module cycloneiv_lcell_comb
|
|||
parameter lpm_type = "cycloneiv_lcell_comb";
|
||||
parameter sum_lutc_input = "datac";
|
||||
|
||||
reg cout_tmp;
|
||||
reg combout_tmp;
|
||||
|
||||
reg [1:0] isum_lutc_input;
|
||||
|
||||
wire dataa_in;
|
||||
wire datab_in;
|
||||
wire datac_in;
|
||||
wire datad_in;
|
||||
wire cin_in;
|
||||
|
||||
// Simulation model of 4-input LUT
|
||||
function lut4;
|
||||
input [15:0] mask;
|
||||
input dataa, datab, datac, datad;
|
||||
reg [7:0] s3;
|
||||
reg [3:0] s2;
|
||||
reg [1:0] s1;
|
||||
begin
|
||||
s3 = datad ? mask[15:8] : mask[7:0];
|
||||
s2 = datac ? s3[7:4] : s3[3:0];
|
||||
s1 = datab ? s2[3:2] : s2[1:0];
|
||||
lut4 = dataa ? s1[1] : s1[0];
|
||||
end
|
||||
endfunction // lut4
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
if (sum_lutc_input == "datac")
|
||||
isum_lutc_input = 0;
|
||||
else if (sum_lutc_input == "cin")
|
||||
isum_lutc_input = 1;
|
||||
else
|
||||
begin
|
||||
$display ("Error: Invalid sum_lutc_input specified\n");
|
||||
$display ("Time: %0t Instance: %m", $time);
|
||||
isum_lutc_input = 2;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
|
||||
begin
|
||||
|
||||
if (isum_lutc_input == 0) // datac
|
||||
begin
|
||||
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
|
||||
datac_in, datad_in);
|
||||
end
|
||||
else if (isum_lutc_input == 1) // cin
|
||||
begin
|
||||
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
|
||||
cin_in, datad_in);
|
||||
end
|
||||
|
||||
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
|
||||
end
|
||||
|
||||
and (combout, combout_tmp, 1'b1) ;
|
||||
and (cout, cout_tmp, 1'b1) ;
|
||||
endmodule // cycloneiv_lcell_comb
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue