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before some refactoring

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This commit is contained in:
Artur Swiderski 2020-10-31 00:59:48 +01:00
parent 42c5007cf6
commit 7a8efe9f1b
5 changed files with 16 additions and 150 deletions
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2
techlibs/intel_le/common/le_sim.v
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@ -168,8 +168,6 @@ endspecify
wire q0, q1;
//assign q0 = LUT >> sum_lutc_input == "cin" ? {'b0, CI, B, A}:{'b0, C, B, A};
//assign q1 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A};
assign q0 = LUT >> {'b0, CI, B, A};
assign q1 = LUT >> {D, CI, B, A};