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$not now passes test_cell!

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This commit is contained in:
Emil J. Tywoniak 2024-06-19 18:55:40 +02:00
parent 81f783bf62
commit 76102f0bc5
7 changed files with 108 additions and 33 deletions
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2
backends/rtlil/rtlil_backend.cc
View file

@ -106,7 +106,7 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
if (sig.is_chunk()) { if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk(), autoint); dump_sigchunk(f, sig.as_chunk(), autoint);
} else { } else {
f << stringf("{ "); f << stringf("{"); //FIXME this is a hack
for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) { for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
dump_sigchunk(f, *it, false); dump_sigchunk(f, *it, false);
f << stringf(" "); f << stringf(" ");

35
kernel/rtlil.cc
View file

@ -2212,14 +2212,15 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
void RTLIL::Module::remove(RTLIL::Cell *cell) void RTLIL::Module::remove(RTLIL::Cell *cell)
{ {
// TODO is this ok? // TODO monitors are broken when unsetPort is unused here
// for
// while (!cell->connections_.empty()) // while (!cell->connections_.empty())
// cell->unsetPort(cell->connections_.begin()->first); // cell->unsetPort((*cell->connections_.begin()).first);
// //
// log_assert(cells_.count(cell->name) != 0); log_assert(cells_.count(cell->name) != 0);
// log_assert(refcount_cells_ == 0); log_assert(refcount_cells_ == 0);
// cells_.erase(cell->name); cells_.erase(cell->name);
delete cell; delete cell;
} }
@ -2428,8 +2429,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
{ {
RTLIL::Cell *cell = new RTLIL::Cell; RTLIL::Cell *cell = new RTLIL::Cell;
std::cout << "RTLIL::Module::addCell " << name.c_str() << " " << type.c_str() << "to module " << this->name.c_str() << "\n"; // std::cout << "RTLIL::Module::addCell " << name.c_str() << " " << type.c_str() << "to module " << this->name.c_str() << "\n";
log("ptr 0x%016X\n", cell);
cell->name = name; cell->name = name;
cell->type = type; cell->type = type;
if (RTLIL::Cell::is_legacy_type(type)) { if (RTLIL::Cell::is_legacy_type(type)) {
@ -2459,7 +2459,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other) RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
{ {
RTLIL::Cell *cell = addCell(name, other->type); RTLIL::Cell *cell = addCell(name, other->type);
cell->module = this;
cell->connections_ = other->connections_; cell->connections_ = other->connections_;
cell->parameters = other->parameters; cell->parameters = other->parameters;
cell->attributes = other->attributes; cell->attributes = other->attributes;
@ -3543,7 +3542,10 @@ void RTLIL::Cell::setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal
} }
} }
static const SigSpec discon_dummy;
const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) const { const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) const {
// log("getPort this %d %s (%016X %016X)\n", this, portname.c_str(), &portname, portname.c_str());
if (is_legacy()) if (is_legacy())
return legacy->getPort(portname); return legacy->getPort(portname);
@ -3553,7 +3555,7 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons
} else if (portname == ID::Y) { } else if (portname == ID::Y) {
return not_.y; return not_.y;
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getPort()");
} }
} else if (type == ID($pos)) { } else if (type == ID($pos)) {
if (portname == ID::A) { if (portname == ID::A) {
@ -3561,7 +3563,7 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons
} else if (portname == ID::Y) { } else if (portname == ID::Y) {
return pos.y; return pos.y;
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getPort()");
} }
} else if (type == ID($neg)) { } else if (type == ID($neg)) {
if (portname == ID::A) { if (portname == ID::A) {
@ -3569,10 +3571,10 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons
} else if (portname == ID::Y) { } else if (portname == ID::Y) {
return neg.y; return neg.y;
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getPort()");
} }
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getPort()");
} }
} }
RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) { RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
@ -3585,7 +3587,7 @@ RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
} else if (portname == ID::Y) { } else if (portname == ID::Y) {
return not_.y; return not_.y;
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getMutPort()");
} }
} else if (type == ID($pos)) { } else if (type == ID($pos)) {
if (portname == ID::A) { if (portname == ID::A) {
@ -3593,7 +3595,7 @@ RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
} else if (portname == ID::Y) { } else if (portname == ID::Y) {
return pos.y; return pos.y;
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getMutPort()");
} }
} else if (type == ID($neg)) { } else if (type == ID($neg)) {
if (portname == ID::A) { if (portname == ID::A) {
@ -3601,10 +3603,10 @@ RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
} else if (portname == ID::Y) { } else if (portname == ID::Y) {
return neg.y; return neg.y;
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getMutPort()");
} }
} else { } else {
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::getMutPort()");
} }
} }
@ -3653,7 +3655,6 @@ void RTLIL::Cell::setParam(const RTLIL::IdString &paramname, RTLIL::Const value)
const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const { const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const {
if (is_legacy()) if (is_legacy())
return legacy->getParam(paramname); return legacy->getParam(paramname);
log_debug("fr");
if (type == ID($not)) { if (type == ID($not)) {
if (paramname == ID::A_WIDTH) { if (paramname == ID::A_WIDTH) {

92
kernel/rtlil.h
View file

@ -1707,7 +1707,7 @@ public:
// but we rely on RTLIL::Cell always being constructed correctly // but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker // since its layout is fixed as defined by InternalOldCellChecker
RTLIL::Const& operator[](RTLIL::IdString name) { RTLIL::Const& operator[](RTLIL::IdString name) {
log("operator[] on %s type %s\n", name.c_str(), parent->type.c_str()); // log("operator[] on %s type %s\n", name.c_str(), parent->type.c_str());
return parent->getMutParam(name); return parent->getMutParam(name);
} }
void operator=(dict<IdString, Const> from) { void operator=(dict<IdString, Const> from) {
@ -1724,6 +1724,26 @@ public:
throw std::out_of_range("Cell::getParam()"); throw std::out_of_range("Cell::getParam()");
} }
} }
void operator=(const FakeParams& from) {
log_assert(parent->type == from.parent->type);
if (parent->is_legacy()) {
log_assert(from.parent->is_legacy());
parent->legacy->parameters = from.parent->legacy->parameters;
// return;
}
auto this_it = begin();
auto from_it = from.parent->parameters.begin();
while (this_it != end() && from_it != from.parent->parameters.end()) {
// Well-ordered
log_assert((*this_it).first == (*from_it).first);
(*this_it).second = (*from_it).second;
++this_it;
++from_it;
}
// Same params
log_assert(this_it == this->end() && from_it == from.parent->parameters.end());
}
bool operator==(const FakeParams& other) const { bool operator==(const FakeParams& other) const {
auto this_it = this->begin(); auto this_it = this->begin();
auto other_it = other.begin(); auto other_it = other.begin();
@ -1742,7 +1762,7 @@ public:
bool operator!=(const FakeParams& other) const { bool operator!=(const FakeParams& other) const {
return !operator==(other); return !operator==(other);
} }
int count(RTLIL::IdString name) const { int count(const RTLIL::IdString& name) const {
try { try {
parent->getParam(name); parent->getParam(name);
} catch (const std::out_of_range& e) { } catch (const std::out_of_range& e) {
@ -1952,12 +1972,14 @@ public:
// but we rely on RTLIL::Cell always being constructed correctly // but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker // since its layout is fixed as defined by InternalOldCellChecker
RTLIL::SigSpec& operator[](RTLIL::IdString portname) { RTLIL::SigSpec& operator[](RTLIL::IdString portname) {
log("operator[] on %s type %s\n", portname.c_str(), parent->type.c_str()); // log("operator[] on %s type %s\n", portname.c_str(), parent->type.c_str());
return parent->getMutPort(portname); return parent->getMutPort(portname);
} }
void operator=(dict<IdString, SigSpec> from) { void operator=(dict<IdString, SigSpec> from) {
if (parent->is_legacy()) if (parent->is_legacy()) {
parent->legacy->connections_ = from; parent->legacy->connections_ = from;
return;
}
if (parent->type == ID($not)) { if (parent->type == ID($not)) {
parent->not_.conns_from_dict(from); parent->not_.conns_from_dict(from);
@ -1969,6 +1991,26 @@ public:
throw std::out_of_range("Cell::getParam()"); throw std::out_of_range("Cell::getParam()");
} }
} }
void operator=(const FakeConns& from) {
log_assert(parent->type == from.parent->type);
if (parent->is_legacy()) {
log_assert(from.parent->is_legacy());
parent->legacy->connections_ = from.parent->legacy->connections_;
// return;
}
auto this_it = begin();
auto from_it = from.parent->connections_.begin();
while (this_it != end() && from_it != from.parent->connections_.end()) {
// Well-ordered
log_assert((*this_it).first == (*from_it).first);
(*this_it).second = (*from_it).second;
++this_it;
++from_it;
}
// Same params
log_assert(this_it == this->end() && from_it == from.parent->connections_.end());
}
bool operator==(const FakeConns& other) const { bool operator==(const FakeConns& other) const {
auto this_it = this->begin(); auto this_it = this->begin();
auto other_it = other.begin(); auto other_it = other.begin();
@ -1987,12 +2029,15 @@ public:
bool operator!=(const FakeConns& other) const { bool operator!=(const FakeConns& other) const {
return !operator==(other); return !operator==(other);
} }
int count(RTLIL::IdString portname) const { int count(const RTLIL::IdString& portname) const {
log("count this %d\n", this);
try { try {
parent->getPort(portname); parent->getPort(portname);
} catch (const std::out_of_range& e) { } catch (const std::out_of_range& e) {
log("count 0\n");
return 0; return 0;
} }
log("count 1\n");
return 1; return 1;
} }
size_t size() const { size_t size() const {
@ -2213,20 +2258,41 @@ public:
const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const; const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;
RTLIL::SigSpec &getMutPort(const RTLIL::IdString &portname); RTLIL::SigSpec &getMutPort(const RTLIL::IdString &portname);
bool hasPort(const RTLIL::IdString &portname) const { bool hasPort(const RTLIL::IdString &portname) const {
// TODO hack? if (is_legacy()) {
return connections_.count(portname) && !getPort(portname).empty(); return legacy->hasPort(portname);
} else if (type == ID($pos)) {
return portname.in(ID::A, ID::Y) && !getPort(portname).empty();
} else if (type == ID($neg)) {
return portname.in(ID::A, ID::Y) && !getPort(portname).empty();
} else if (type == ID($not)) {
return portname.in(ID::A, ID::Y) && !getPort(portname).empty();
} else {
throw std::out_of_range("FakeParams::size()");
}
}
void unsetPort(const RTLIL::IdString& portname) {
if (is_legacy())
legacy->unsetPort(portname);
setPort(portname, SigSpec());
} }
// The need for this function implies setPort will be used on incompat types
void unsetPort(const RTLIL::IdString& portname) { (void)portname; }
void setParam(const RTLIL::IdString &paramname, RTLIL::Const value); void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
// TODO is this reasonable at all? // TODO is this reasonable at all?
const RTLIL::Const& getParam(const RTLIL::IdString &paramname) const; const RTLIL::Const& getParam(const RTLIL::IdString &paramname) const;
RTLIL::Const& getMutParam(const RTLIL::IdString &paramname); RTLIL::Const& getMutParam(const RTLIL::IdString &paramname);
bool hasParam(const RTLIL::IdString &paramname) const { bool hasParam(const RTLIL::IdString &paramname) const {
return parameters.count(paramname) && !getParam(paramname).empty(); if (is_legacy()) {
return legacy->hasParam(paramname);
} else if (type.in(ID($pos), ID($neg), ID($not))) {
return paramname.in(ID::A_WIDTH, ID::Y_WIDTH, ID::A_SIGNED) && !getParam(paramname).empty();
} else {
throw std::out_of_range("FakeParams::size()");
}
}
void unsetParam(const RTLIL::IdString& paramname) {
if (is_legacy())
legacy->unsetParam(paramname);
setPort(paramname, Const());
} }
// The need for this function implies setPort will be used on incompat types
void unsetParam(const RTLIL::IdString& paramname) { (void)paramname; }
template<typename T> template<typename T>
void rewrite_sigspecs2(T &functor) { void rewrite_sigspecs2(T &functor) {
// for(auto it = connections_.begin(); it != connections_.end(); ++it) { // for(auto it = connections_.begin(); it != connections_.end(); ++it) {
@ -2252,7 +2318,7 @@ public:
private: private:
// NOT the tag, but a helper - faster short-circuit if public? // NOT the tag, but a helper - faster short-circuit if public?
static bool is_legacy_type (RTLIL::IdString type) { static bool is_legacy_type (RTLIL::IdString type) {
return !type.in(ID($not), ID($pos), ID($neg)); return !type.in(ID($not), ID($pos));
} }
}; };

2
passes/opt/opt_expr.cc
View file

@ -409,7 +409,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto cell : module->cells()) for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') { if (design->selected(module, cell) && cell->type[0] == '$') {
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
GetSize(cell->getPort(ID::B)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A)); invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
if (cell->type.in(ID($mux), ID($_MUX_)) && if (cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0)) cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))

2
passes/opt/opt_merge.cc
View file

@ -167,7 +167,7 @@ struct OptMergeWorker
if (!cell2->connections_.count(it.first)) if (!cell2->connections_.count(it.first))
return false; return false;
decltype(Cell::connections_) conn1, conn2; dict<RTLIL::IdString, RTLIL::SigSpec> conn1, conn2;
conn1.reserve(cell1->connections_.size()); conn1.reserve(cell1->connections_.size());
conn2.reserve(cell1->connections_.size()); conn2.reserve(cell1->connections_.size());

7
passes/techmap/alumacc.cc
View file

@ -145,7 +145,9 @@ struct AlumaccWorker
Macc::port_t new_port; Macc::port_t new_port;
n->cell = cell; n->cell = cell;
log("%s\n", log_signal(cell->getPort(ID::Y)));
n->y = sigmap(cell->getPort(ID::Y)); n->y = sigmap(cell->getPort(ID::Y));
log("%s\n", log_signal(n->y));
n->users = 0; n->users = 0;
for (auto bit : n->y) for (auto bit : n->y)
@ -181,6 +183,7 @@ struct AlumaccWorker
n->macc.ports.push_back(new_port); n->macc.ports.push_back(new_port);
} }
log("%s\n", log_signal(n->y));
log_assert(sig_macc.count(n->y) == 0); log_assert(sig_macc.count(n->y) == 0);
sig_macc[n->y] = n; sig_macc[n->y] = n;
} }
@ -237,8 +240,12 @@ struct AlumaccWorker
for (int i = 0; i < GetSize(n->macc.ports); i++) for (int i = 0; i < GetSize(n->macc.ports); i++)
{ {
log("ports: size %d\n", n->macc.ports.size());
auto &port = n->macc.ports[i]; auto &port = n->macc.ports[i];
log("ports 2: size %d\n", port.in_b.size());
log("uuh: count %d\n", sig_macc.count(port.in_a));
log("%s\n", log_signal(port.in_a));
if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0) if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
continue; continue;

1
passes/techmap/techmap.cc
View file

@ -563,6 +563,7 @@ struct TechmapWorker
if (extmapper_name == "wrap") { if (extmapper_name == "wrap") {
std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
log_module(extmapper_module);
mkdebug.on(); mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
log_continue = true; log_continue = true;