diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index f4f71f01e..8c254c67e 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -106,7 +106,7 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk(), autoint);
 	} else {
-		f << stringf("{ ");
+		f << stringf("{"); //FIXME this is a hack
 		for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
 			dump_sigchunk(f, *it, false);
 			f << stringf(" ");
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 16376fe4b..e222be165 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2212,14 +2212,15 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 
 void RTLIL::Module::remove(RTLIL::Cell *cell)
 {
-	// TODO is this ok?
+	// TODO monitors are broken when unsetPort is unused here
+	// for 
 	// while (!cell->connections_.empty())
-	// 	cell->unsetPort(cell->connections_.begin()->first);
+	// 	cell->unsetPort((*cell->connections_.begin()).first);
 	//
 
-	// log_assert(cells_.count(cell->name) != 0);
-	// log_assert(refcount_cells_ == 0);
-	// cells_.erase(cell->name);
+	log_assert(cells_.count(cell->name) != 0);
+	log_assert(refcount_cells_ == 0);
+	cells_.erase(cell->name);
 	delete cell;
 }
 
@@ -2428,8 +2429,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
 {
 	RTLIL::Cell *cell = new RTLIL::Cell;
-	std::cout << "RTLIL::Module::addCell " << name.c_str() << " " << type.c_str() << "to module " << this->name.c_str() << "\n";
-	log("ptr 0x%016X\n", cell);
+	// std::cout << "RTLIL::Module::addCell " << name.c_str() << " " << type.c_str() << "to module " << this->name.c_str() << "\n";
 	cell->name = name;
 	cell->type = type;
 	if (RTLIL::Cell::is_legacy_type(type)) {
@@ -2459,7 +2459,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
 {
 	RTLIL::Cell *cell = addCell(name, other->type);
-	cell->module = this;
 	cell->connections_ = other->connections_;
 	cell->parameters = other->parameters;
 	cell->attributes = other->attributes;
@@ -3543,7 +3542,10 @@ void RTLIL::Cell::setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal
 	}
 }
 
+static const SigSpec discon_dummy;
+
 const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) const {
+	// log("getPort this %d %s (%016X %016X)\n", this, portname.c_str(), &portname, portname.c_str());
 	if (is_legacy())
 		return legacy->getPort(portname);
 
@@ -3553,7 +3555,7 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons
 		} else if (portname == ID::Y) {
 			return not_.y;
 		} else {
-			throw std::out_of_range("Cell::setPort()");
+			throw std::out_of_range("Cell::getPort()");
 		}
 	} else if (type == ID($pos)) {
 		if (portname == ID::A) {
@@ -3561,7 +3563,7 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons
 		} else if (portname == ID::Y) {
 			return pos.y;
 		} else {
-			throw std::out_of_range("Cell::setPort()");
+			throw std::out_of_range("Cell::getPort()");
 		}
 	} else if (type == ID($neg)) {
 		if (portname == ID::A) {
@@ -3569,10 +3571,10 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons
 		} else if (portname == ID::Y) {
 			return neg.y;
 		} else {
-			throw std::out_of_range("Cell::setPort()");
+			throw std::out_of_range("Cell::getPort()");
 		}
 	} else {
-		throw std::out_of_range("Cell::setPort()");
+		throw std::out_of_range("Cell::getPort()");
 	}
 }
 RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
@@ -3585,7 +3587,7 @@ RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
 		} else if (portname == ID::Y) {
 			return not_.y;
 		} else {
-			throw std::out_of_range("Cell::setPort()");
+			throw std::out_of_range("Cell::getMutPort()");
 		}
 	} else if (type == ID($pos)) {
 		if (portname == ID::A) {
@@ -3593,7 +3595,7 @@ RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
 		} else if (portname == ID::Y) {
 			return pos.y;
 		} else {
-			throw std::out_of_range("Cell::setPort()");
+			throw std::out_of_range("Cell::getMutPort()");
 		}
 	} else if (type == ID($neg)) {
 		if (portname == ID::A) {
@@ -3601,10 +3603,10 @@ RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
 		} else if (portname == ID::Y) {
 			return neg.y;
 		} else {
-			throw std::out_of_range("Cell::setPort()");
+			throw std::out_of_range("Cell::getMutPort()");
 		}
 	} else {
-		throw std::out_of_range("Cell::setPort()");
+		throw std::out_of_range("Cell::getMutPort()");
 	}
 }
 
@@ -3653,7 +3655,6 @@ void RTLIL::Cell::setParam(const RTLIL::IdString &paramname, RTLIL::Const value)
 const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const {
 	if (is_legacy())
 		return legacy->getParam(paramname);
-	log_debug("fr");
 
 	if (type == ID($not)) {
 		if (paramname == ID::A_WIDTH) {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 5a0274286..2ec721c99 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1707,7 +1707,7 @@ public:
 		// but we rely on RTLIL::Cell always being constructed correctly
 		// since its layout is fixed as defined by InternalOldCellChecker
 		RTLIL::Const& operator[](RTLIL::IdString name) {
-			log("operator[] on %s type %s\n", name.c_str(), parent->type.c_str());
+			// log("operator[] on %s type %s\n", name.c_str(), parent->type.c_str());
 			return parent->getMutParam(name);
 		}
 		void operator=(dict<IdString, Const> from) {
@@ -1724,6 +1724,26 @@ public:
 				throw std::out_of_range("Cell::getParam()");
 			}
 		}
+		void operator=(const FakeParams& from) {
+			log_assert(parent->type == from.parent->type);
+
+			if (parent->is_legacy()) {
+				log_assert(from.parent->is_legacy());
+				parent->legacy->parameters = from.parent->legacy->parameters;
+				// return;
+			}
+			auto this_it = begin();
+			auto from_it = from.parent->parameters.begin();
+			while (this_it != end() && from_it != from.parent->parameters.end()) {
+				// Well-ordered
+				log_assert((*this_it).first == (*from_it).first);
+				(*this_it).second = (*from_it).second;
+				++this_it;
+				++from_it;
+			}
+			// Same params
+			log_assert(this_it == this->end() && from_it == from.parent->parameters.end());
+		}
 		bool operator==(const FakeParams& other) const {
 			auto this_it = this->begin();
 			auto other_it = other.begin();
@@ -1742,7 +1762,7 @@ public:
 		bool operator!=(const FakeParams& other) const {
 			return !operator==(other);
 		}
-		int count(RTLIL::IdString name) const {
+		int count(const RTLIL::IdString& name) const {
 			try {
 				parent->getParam(name);
 			} catch (const std::out_of_range& e) {
@@ -1952,12 +1972,14 @@ public:
 		// but we rely on RTLIL::Cell always being constructed correctly
 		// since its layout is fixed as defined by InternalOldCellChecker
 		RTLIL::SigSpec& operator[](RTLIL::IdString portname) {
-			log("operator[] on %s type %s\n", portname.c_str(), parent->type.c_str());
+			// log("operator[] on %s type %s\n", portname.c_str(), parent->type.c_str());
 			return parent->getMutPort(portname);
 		}
 		void operator=(dict<IdString, SigSpec> from) {
-			if (parent->is_legacy())
+			if (parent->is_legacy()) {
 				parent->legacy->connections_ = from;
+				return;
+			}
 
 			if (parent->type == ID($not)) {
 				parent->not_.conns_from_dict(from);
@@ -1969,6 +1991,26 @@ public:
 				throw std::out_of_range("Cell::getParam()");
 			}
 		}
+		void operator=(const FakeConns& from) {
+			log_assert(parent->type == from.parent->type);
+
+			if (parent->is_legacy()) {
+				log_assert(from.parent->is_legacy());
+				parent->legacy->connections_ = from.parent->legacy->connections_;
+				// return;
+			}
+			auto this_it = begin();
+			auto from_it = from.parent->connections_.begin();
+			while (this_it != end() && from_it != from.parent->connections_.end()) {
+				// Well-ordered
+				log_assert((*this_it).first == (*from_it).first);
+				(*this_it).second = (*from_it).second;
+				++this_it;
+				++from_it;
+			}
+			// Same params
+			log_assert(this_it == this->end() && from_it == from.parent->connections_.end());
+		}
 		bool operator==(const FakeConns& other) const {
 			auto this_it = this->begin();
 			auto other_it = other.begin();
@@ -1987,12 +2029,15 @@ public:
 		bool operator!=(const FakeConns& other) const {
 			return !operator==(other);
 		}
-		int count(RTLIL::IdString portname) const {
+		int count(const RTLIL::IdString& portname) const {
+			log("count this %d\n", this);
 			try {
 				parent->getPort(portname);
 			} catch (const std::out_of_range& e) {
+				log("count 0\n");
 				return 0;
 			}
+			log("count 1\n");
 			return 1;
 		}
 		size_t size() const {
@@ -2213,20 +2258,41 @@ public:
 	const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;
 	RTLIL::SigSpec &getMutPort(const RTLIL::IdString &portname);
 	bool hasPort(const RTLIL::IdString &portname) const {
-		// TODO hack?
-		return connections_.count(portname) && !getPort(portname).empty();
+		if (is_legacy()) {
+			return legacy->hasPort(portname);
+		} else if (type == ID($pos)) {
+			return portname.in(ID::A, ID::Y) && !getPort(portname).empty();
+		} else if (type == ID($neg)) {
+			return portname.in(ID::A, ID::Y) && !getPort(portname).empty();
+		} else if (type == ID($not)) {
+			return portname.in(ID::A, ID::Y) && !getPort(portname).empty();
+		} else {
+			throw std::out_of_range("FakeParams::size()");
+		}
+	}
+	void unsetPort(const RTLIL::IdString& portname) {
+		if (is_legacy())
+			legacy->unsetPort(portname);
+		setPort(portname, SigSpec());
 	}
-	// The need for this function implies setPort will be used on incompat types
-	void unsetPort(const RTLIL::IdString& portname) { (void)portname; }
 	void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
 	// TODO is this reasonable at all?
 	const RTLIL::Const& getParam(const RTLIL::IdString &paramname) const;
 	RTLIL::Const& getMutParam(const RTLIL::IdString &paramname);
 	bool hasParam(const RTLIL::IdString &paramname) const {
-		return parameters.count(paramname) && !getParam(paramname).empty();
+		if (is_legacy()) {
+			return legacy->hasParam(paramname);
+		} else if (type.in(ID($pos), ID($neg), ID($not))) {
+			return paramname.in(ID::A_WIDTH, ID::Y_WIDTH, ID::A_SIGNED) && !getParam(paramname).empty();
+		} else {
+			throw std::out_of_range("FakeParams::size()");
+		}
+	}
+	void unsetParam(const RTLIL::IdString& paramname) {
+		if (is_legacy())
+			legacy->unsetParam(paramname);
+		setPort(paramname, Const());
 	}
-	// The need for this function implies setPort will be used on incompat types
-	void unsetParam(const RTLIL::IdString& paramname) { (void)paramname; }
 	template<typename T>
 	void rewrite_sigspecs2(T &functor) {
 		// for(auto it = connections_.begin(); it != connections_.end(); ++it) {
@@ -2252,7 +2318,7 @@ public:
 private:
 	// NOT the tag, but a helper - faster short-circuit if public?
 	static bool is_legacy_type (RTLIL::IdString type) {
-		return !type.in(ID($not), ID($pos), ID($neg));
+		return !type.in(ID($not), ID($pos));
 	}
 
 };
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index ab6c792aa..ecf0d2c99 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -409,7 +409,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	for (auto cell : module->cells())
 		if (design->selected(module, cell) && cell->type[0] == '$') {
 			if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
-					GetSize(cell->getPort(ID::B)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
+					GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
 				invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
 			if (cell->type.in(ID($mux), ID($_MUX_)) &&
 					cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 743d2af0a..214deae4b 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -167,7 +167,7 @@ struct OptMergeWorker
 			if (!cell2->connections_.count(it.first))
 				return false;
 
-		decltype(Cell::connections_) conn1, conn2;
+		dict<RTLIL::IdString, RTLIL::SigSpec> conn1, conn2;
 		conn1.reserve(cell1->connections_.size());
 		conn2.reserve(cell1->connections_.size());
 
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index e16256707..a5b5e913b 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -145,7 +145,9 @@ struct AlumaccWorker
 			Macc::port_t new_port;
 
 			n->cell = cell;
+			log("%s\n", log_signal(cell->getPort(ID::Y)));
 			n->y = sigmap(cell->getPort(ID::Y));
+			log("%s\n", log_signal(n->y));
 			n->users = 0;
 
 			for (auto bit : n->y)
@@ -181,6 +183,7 @@ struct AlumaccWorker
 				n->macc.ports.push_back(new_port);
 			}
 
+			log("%s\n", log_signal(n->y));
 			log_assert(sig_macc.count(n->y) == 0);
 			sig_macc[n->y] = n;
 		}
@@ -237,8 +240,12 @@ struct AlumaccWorker
 
 				for (int i = 0; i < GetSize(n->macc.ports); i++)
 				{
+					log("ports: size %d\n", n->macc.ports.size());
 					auto &port = n->macc.ports[i];
 
+					log("ports 2: size %d\n", port.in_b.size());
+					log("uuh: count %d\n", sig_macc.count(port.in_a));
+					log("%s\n", log_signal(port.in_a));
 					if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
 						continue;
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index f7ebb5b15..a33187954 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -563,6 +563,7 @@ struct TechmapWorker
 							if (extmapper_name == "wrap") {
 								std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
 								log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
+								log_module(extmapper_module);
 								mkdebug.on();
 								Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
 								log_continue = true;