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cells can now be created, techmap broken

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This commit is contained in:
Emil J. Tywoniak 2024-06-18 19:16:48 +02:00
parent b190055bbb
commit 81f783bf62
3 changed files with 19 additions and 49 deletions
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47
kernel/rtlil.cc
View file

@ -2425,20 +2425,6 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
return wire;
}
template<typename AAAA>
void scream(AAAA* aaa) {
unsigned char *ptr = reinterpret_cast<unsigned char*>(aaa);
for (size_t i = 0; i < sizeof(AAAA); ++i) {
std::cout << std::hex << std::setw(2) << std::setfill('0') << static_cast<int>(ptr[i]) << ' ';
}
std::cout << std::endl;
}
template<typename AAAA>
void scream(const char* ctx, AAAA* aaa) {
log("%s\n", ctx);
scream(aaa);
}
RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
{
RTLIL::Cell *cell = new RTLIL::Cell;
@ -2446,7 +2432,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
log("ptr 0x%016X\n", cell);
cell->name = name;
cell->type = type;
// scream("addCell pre", cell);
if (RTLIL::Cell::is_legacy_type(type)) {
cell->legacy = new RTLIL::OldCell;
cell->legacy->name = name;
@ -2457,14 +2442,16 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
// Due to the tagged union deal,
// we don't get this automagically,
// so let's use "placement new"
for (auto param: cell->parameters) {
new (&param.second) Const();
}
for (auto conn: cell->connections_) {
new (&conn.second) SigSpec();
if (type == ID($not)) {
new (&cell->not_) Unary();
} else if (type == ID($pos)) {
new (&cell->pos) Unary();
} else if (type == ID($neg)) {
new (&cell->neg) Unary();
} else {
throw std::out_of_range("Cell::setPort()");
}
}
// scream("addCell post", cell);
add(cell);
return cell;
}
@ -3630,31 +3617,31 @@ void RTLIL::Cell::setParam(const RTLIL::IdString &paramname, RTLIL::Const value)
if (type == ID($not)) {
if (paramname == ID::A_WIDTH) {
not_.a_width = value.as_int();
not_.a_width = value;
} else if (paramname == ID::Y_WIDTH) {
not_.y_width = value.as_int();
not_.y_width = value;
} else if (paramname == ID::A_SIGNED) {
not_.is_signed = value.as_int();
not_.is_signed = value;
} else {
throw std::out_of_range("Cell::setParam()");
}
} else if (type == ID($pos)) {
if (paramname == ID::A_WIDTH) {
pos.a_width = value.as_int();
pos.a_width = value;
} else if (paramname == ID::Y_WIDTH) {
pos.y_width = value.as_int();
pos.y_width = value;
} else if (paramname == ID::A_SIGNED) {
pos.is_signed = value.as_int();
pos.is_signed = value;
} else {
throw std::out_of_range("Cell::setParam()");
}
} else if (type == ID($neg)) {
if (paramname == ID::A_WIDTH) {
neg.a_width = value.as_int();
neg.a_width = value;
} else if (paramname == ID::Y_WIDTH) {
neg.y_width = value.as_int();
neg.y_width = value;
} else if (paramname == ID::A_SIGNED) {
neg.is_signed = value.as_int();
neg.is_signed = value;
} else {
throw std::out_of_range("Cell::setParam()");
}

17
kernel/rtlil.h
View file

@ -1625,7 +1625,7 @@ struct RTLIL::Unary {
return {std::make_pair(ID::A, std::ref(a)), std::make_pair(ID::Y, std::ref(y))};
}
std::array<std::pair<IdString, Const&>, 3> parameters() {
return {std::make_pair(ID::A_WIDTH, std::ref(a_width)), std::make_pair(ID::Y_WIDTH, std::ref(y_width)), std::make_pair(ID::A_SIGNED, std::ref(y_width))};
return {std::make_pair(ID::A_WIDTH, std::ref(a_width)), std::make_pair(ID::Y_WIDTH, std::ref(y_width)), std::make_pair(ID::A_SIGNED, std::ref(is_signed))};
}
bool input(IdString portname) const {
return portname == ID::A;
@ -1671,20 +1671,7 @@ public:
struct FakeParams {
RTLIL::Cell* parent;
RTLIL::Const& at(RTLIL::IdString paramname) {
if (parent->is_legacy())
return parent->legacy->parameters.at(paramname);
if (parent->type == ID($not)) {
if (paramname == ID::A_WIDTH) {
return parent->not_.a_width;
} else if (paramname == ID::Y_WIDTH) {
return parent->not_.y_width;
} else {
throw std::out_of_range("Cell::getParam()");
}
} else {
throw std::out_of_range("Cell::getParam()");
}
return parent->getMutParam(paramname);
}
const RTLIL::Const& at(RTLIL::IdString name) const {
return parent->getParam(name);

4
passes/tests/test_cell.cc
View file

@ -41,10 +41,6 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
{
RTLIL::Module *module = design->addModule(ID(gold));
RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type);
for (auto para : cell->parameters)
log("param %s is %s\n", para.first.c_str(), para.second.as_string().c_str());
// for (auto para : cell->connections)
// log("param %s is %s\n", para.first.c_str(), para.second.as_string());
RTLIL::Wire *wire;
if (cell_type.in(ID($mux), ID($pmux)))