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$not now passes test_cell!
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parent
81f783bf62
commit
76102f0bc5
7 changed files with 108 additions and 33 deletions
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@ -409,7 +409,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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for (auto cell : module->cells())
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if (design->selected(module, cell) && cell->type[0] == '$') {
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if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
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GetSize(cell->getPort(ID::B)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
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GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
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invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
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if (cell->type.in(ID($mux), ID($_MUX_)) &&
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cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
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@ -167,7 +167,7 @@ struct OptMergeWorker
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if (!cell2->connections_.count(it.first))
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return false;
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decltype(Cell::connections_) conn1, conn2;
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dict<RTLIL::IdString, RTLIL::SigSpec> conn1, conn2;
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conn1.reserve(cell1->connections_.size());
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conn2.reserve(cell1->connections_.size());
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