Merge pull request #4854 from YosysHQ/krys/cutpoint_blackbox

Add -blackbox option to cutpoint pass

kernel/rtlil.cc

@@ -2140,7 +2140,7 @@ namespace {
 				param(ID::TYPE);
 				check_expected();
 				std::string scope_type = cell->getParam(ID::TYPE).decode_string();
-				if (scope_type != "module" && scope_type != "struct")
+				if (scope_type != "module" && scope_type != "struct" && scope_type != "blackbox")
 					error(__LINE__);
 				return;
 			}

passes/hierarchy/hierarchy.cc

@@ -978,6 +978,11 @@ struct HierarchyPass : public Pass {
 			}
 		}
 
+		bool verific_mod = false;
+#ifdef YOSYS_ENABLE_VERIFIC
+		verific_mod = verific_import_pending;
+#endif
+
 		if (top_mod == nullptr && !load_top_mod.empty()) {
 #ifdef YOSYS_ENABLE_VERIFIC
 			if (verific_import_pending) {
@@ -1418,13 +1423,18 @@ struct HierarchyPass : public Pass {
 				if (m == nullptr)
 					continue;
 
-				if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
-					IdString new_m_name = m->derive(design, cell->parameters, true);
-					if (new_m_name.empty())
-						continue;
-					if (new_m_name != m->name) {
-						m = design->module(new_m_name);
-						blackbox_derivatives.insert(m);
+				bool boxed_params = false;
+				if (m->get_blackbox_attribute() && !cell->parameters.empty()) {
+					if (m->get_bool_attribute(ID::dynports)) {
+						IdString new_m_name = m->derive(design, cell->parameters, true);
+						if (new_m_name.empty())
+							continue;
+						if (new_m_name != m->name) {
+							m = design->module(new_m_name);
+							blackbox_derivatives.insert(m);
+						}
+					} else {
+						boxed_params = true;
 					}
 				}
 
@@ -1440,8 +1450,12 @@ struct HierarchyPass : public Pass {
 
 					SigSpec sig = conn.second;
 
-					if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
-					{
+					bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second);
+					if (resize_widths && verific_mod && boxed_params)
+						log_warning("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n",
+								log_id(module), log_id(cell), log_id(conn.first)
+						);
+					else if (resize_widths) {
 						if (GetSize(w) < GetSize(conn.second))
 						{
 							int n = GetSize(conn.second) - GetSize(w);

passes/sat/cutpoint.cc

@@ -37,10 +37,20 @@ struct CutpointPass : public Pass {
 		log("        set cutpoint nets to undef (x). the default behavior is to create\n");
 		log("        an $anyseq cell and drive the cutpoint net from that\n");
 		log("\n");
+		log("    -noscopeinfo\n");
+		log("        do not create '$scopeinfo' cells that preserve attributes of cells that\n");
+		log("        were removed by this pass\n");
+		log("\n");
+		log("    cutpoint -blackbox [options]\n");
+		log("\n");
+		log("Replace all instances of blackboxes in the design with a formal cut point.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		 bool flag_undef = false;
+		bool flag_undef = false;
+		bool flag_scopeinfo = true;
+		bool flag_blackbox = false;
 
 		log_header(design, "Executing CUTPOINT pass.\n");
 
@@ -51,26 +61,31 @@ struct CutpointPass : public Pass {
 				flag_undef = true;
 				continue;
 			}
+			if (args[argidx] == "-noscopeinfo") {
+				flag_scopeinfo = false;
+				continue;
+			}
+			if (args[argidx] == "-blackbox") {
+				flag_blackbox = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
-		for (auto module : design->selected_modules())
-		{
-			if (module->is_selected_whole()) {
-				log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
-				module->new_connections(std::vector<RTLIL::SigSig>());
-				for (auto cell : vector<Cell*>(module->cells()))
-					module->remove(cell);
-				vector<Wire*> output_wires;
-				for (auto wire : module->wires())
-					if (wire->port_output)
-						output_wires.push_back(wire);
-				for (auto wire : output_wires)
-					module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
-				continue;
-			}
+		if (flag_blackbox) {
+			if (!design->full_selection())
+				log_cmd_error("This command only operates on fully selected designs!\n");
+			design->push_empty_selection();
+			auto &selection = design->selection();
+			for (auto module : design->modules())
+				for (auto cell : module->cells())
+					if (selection.boxed_module(cell->type))
+						selection.select(module, cell);
+		}
 
+		for (auto module : design->all_selected_modules())
+		{
 			SigMap sigmap(module);
 			pool<SigBit> cutpoint_bits;
 
@@ -82,7 +97,26 @@ struct CutpointPass : public Pass {
 					if (cell->output(conn.first))
 						module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
 				}
+
+				RTLIL::Cell *scopeinfo = nullptr;
+				auto cell_name = cell->name;
+				if (flag_scopeinfo && cell_name.isPublic()) {
+					auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
+					scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
+
+					for (auto const &attr : cell->attributes)
+					{
+						if (attr.first == ID::hdlname)
+							scopeinfo->attributes.insert(attr);
+						else
+							scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second);
+					}
+				}
+
 				module->remove(cell);
+
+				if (scopeinfo != nullptr)
+					module->rename(scopeinfo, cell_name);
 			}
 
 			for (auto wire : module->selected_wires()) {

tests/various/.gitignore

@@ -1,5 +1,6 @@
 /*.log
 /*.out
+/*.sel
 /write_gzip.v
 /write_gzip.v.gz
 /run-test.mk

tests/various/cutpoint_blackbox.ys

@@ -0,0 +1,72 @@
+read_verilog -specify << EOT
+module top(input a, b, output o);
+    wire c, d, e;
+    bb #(.SOME_PARAM(1)) bb1 (.a (a), .b (b), .o (c));
+    bb #(.SOME_PARAM(2)) bb2 (.a (a), .b (b), .o (d));
+    wb wb1 (.a (a), .b (b), .o (e));
+    some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
+endmodule
+
+(* blackbox *)
+module bb #( parameter SOME_PARAM=0 ) (input a, b, output o);
+assign o = a | b;
+specify
+	(a => o) = 1;
+endspecify
+endmodule
+
+(* whitebox *)
+module wb(input a, b, output o);
+assign o = a ^ b;
+endmodule
+
+module some_mod(input a, b, c, output o);
+assign o = a & (b | c);
+endmodule
+EOT
+
+hierarchy -top top
+design -save hier
+
+select -assert-none t:$anyseq
+select -assert-count 3 =t:?b
+cutpoint -blackbox
+
+select -assert-none =t:?b
+select -assert-none r:SOME_PARAM
+
+select -assert-count 3 t:$anyseq
+select -assert-count 3 t:$scopeinfo
+select -assert-count 3 t:$scopeinfo r:TYPE=blackbox %i
+select -assert-count 3 t:$scopeinfo n:*cutpoint.cc* %i
+
+# -noscopeinfo works with -blackbox
+design -load hier
+cutpoint -blackbox -noscopeinfo
+select -assert-none t:$scopeinfo
+
+# cutpoint -blackbox === cutpoint =A:whitebox =A:blackbox %u %C
+#                        (simplified to =A:*box %C)
+design -load hier
+cutpoint -blackbox
+rename -enumerate -pattern A_% t:$scopeinfo
+rename -enumerate -pattern B_% t:$anyseq
+rename -enumerate -pattern C_% w:*Anyseq*
+design -save gold
+select -write cutpoint.gold.sel =*
+
+design -load hier
+cutpoint =A:*box %C
+rename -enumerate -pattern A_% t:$scopeinfo
+rename -enumerate -pattern B_% t:$anyseq
+rename -enumerate -pattern C_% w:*Anyseq*
+design -save gate
+select -write cutpoint.gate.sel
+select -read cutpoint.gold.sel
+# nothing in gate but not gold
+select -assert-none % %n
+
+design -load gold
+select -read cutpoint.gate.sel
+# nothing in gold but not gate
+select -assert-none % %n