mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
10 lines
363 B
Plaintext
10 lines
363 B
Plaintext
read_verilog ../common/mul.v
|
|
hierarchy -top top
|
|
proc
|
|
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 1 t:DSP48E1
|
|
select -assert-none t:DSP48E1 %% t:* %D
|