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https://github.com/YosysHQ/yosys
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minor progress in mapping
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parent
309689da5b
commit
53a95de62f
3 changed files with 21 additions and 14 deletions
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@ -170,7 +170,6 @@ struct SynthIntelLEPass : public ScriptPass {
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run(stringf("read_verilog -sv -lib +/intel_le/%s/cells_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/le_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dff_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dsp_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/mem_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s -icells +/intel_le/common/abc9_model.v", family_opt.c_str()));
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@ -196,11 +195,11 @@ struct SynthIntelLEPass : public ScriptPass {
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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run("alumacc");
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run("techmap -map +/intel_le/common/arith_le_map.v -map +/intel_le/common/dsp_map.v");
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run("techmap -map +/intel_le/common/arith_le_map.v");
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run("opt");
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run("memory -nomap");
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run("opt_clean");
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@ -227,7 +226,7 @@ struct SynthIntelLEPass : public ScriptPass {
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if (check_label("map_luts")) {
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run("techmap -map +/intel_le/common/abc9_map.v");
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run(stringf("abc9 %s -maxlut 6 -W 600", help_mode ? "[-dff]" : dff ? "-dff" : ""));
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run(stringf("abc9 %s -maxlut 4 -W 400", help_mode ? "[-dff]" : dff ? "-dff" : ""));
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run("techmap -map +/intel_le/common/abc9_unmap.v");
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run("techmap -map +/intel_le/common/le_map.v");
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run("opt -fast");
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