mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-22 16:45:32 +00:00
minor cleanup and fixes
This commit is contained in:
Artur Swiderski
parent
41f83c19fd
commit
309689da5b
11 changed files with 76 additions and 355 deletions
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@ -10,15 +10,12 @@ $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/le_s
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/arith_le_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_sim.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_sim.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/mem_sim.v))
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$(eval $(call add_share_file,share/intel_le/cycloneiv,techlibs/intel_le/cycloneiv/cells_sim.v))
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# RAM
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m9k.txt))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m20k_map.v))
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# Miscellaneous
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/megafunction_bb.v))
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@ -30,21 +30,21 @@ wire [Y_WIDTH-1:0] AA = A_buf;
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BX = B_buf;
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wire [Y_WIDTH-1:0] BSUM;
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wire [Y_WIDTH-1:0] BTOADDER;
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wire [Y_WIDTH:0] LE_CARRY;
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// Start of carry chain
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generate
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if (_TECHMAP_CONSTMSK_CI_ == 1) begin
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assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
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assign LE_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
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end else begin
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MISTRAL_ALUT_ARITH #(
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.LUT0(16'b1010_1010_1010_1010), // Q = A
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.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
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.LUT(16'b1010_1010_1010_1010), // Q = A
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) alm_start (
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.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
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.CI(1'b0),
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.CO(ALM_CARRY[0])
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.SO(),
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.CO(LE_CARRY[0])
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);
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end
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endgenerate
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@ -54,25 +54,24 @@ genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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// TODO: mwk suggests that a pass could merge pre-adder logic into this.
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MISTRAL_ALUT_ARITH #(
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.LUT0(16'b0110_0110_0110_0110) // Q = A ? ~B : B
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.LUT(16'b0110_0110_0110_0110) // Q = A ? ~B : B
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) alm_i (
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.A(BI), .B(BX[i]), .C(1'b0), .D(1'b0),
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.CI(1'b0),
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.SO(BSUM[i]),
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.SO(BTOADDER[i]),
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.CO()
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);
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MISTRAL_ALUT_ARITH #(
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.LUT0(16'b1010_1010_1010_1010), // SUM = A xor B xor CI
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.LUT(16'b1010_1010_1010_1010), // SUM = A xor B xor CI
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// CARRYi+1 = A and B or A and CI or B and CI
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.sum_lutc_input("cin")
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) alm_start (
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.A(AA[i]), .B(BX[i]), .C(1'b1), .D(1'b1),
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.CI(LE_CARRY),
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.A(AA[i]), .B(BTOADDER[i]), .C(1'b1), .D(1'b1),
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.CI(LE_CARRY[i]),
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.SO(Y[i]),
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.CO(ALM_CARRY[i+1])
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.CO(LE_CARRY[i+1])
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);
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// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
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assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
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end endgenerate
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assign X = AA ^ BB;
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@ -1,33 +0,0 @@
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bram __MISTRAL_M20K_SDP
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init 1 # TODO: Re-enable when I figure out how BRAM init works
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abits 14 @D16384x1
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dbits 1 @D16384x1
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abits 13 @D8192x2
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dbits 2 @D8192x2
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abits 12 @D4096x4 @D4096x5
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dbits 4 @D4096x4
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dbits 5 @D4096x5
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abits 11 @D2048x8 @D2048x10
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dbits 8 @D2048x8
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dbits 10 @D2048x10
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abits 10 @D1024x16 @D1024x20
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dbits 16 @D1024x16
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dbits 20 @D1024x20
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abits 9 @D512x32 @D512x40
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dbits 32 @D512x32
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dbits 40 @D512x40
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groups 2
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ports 1 1
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wrmode 1 0
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# read enable; write enable + byte enables (only for multiples of 8)
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enable 1 1
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transp 0 0
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clocks 1 1
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clkpol 1 1
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endbram
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match __MISTRAL_M20K_SDP
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min efficiency 5
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make_transp
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endmatch
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@ -1,31 +0,0 @@
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module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 20;
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parameter CFG_ENABLE_A = 1;
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parameter CFG_ENABLE_B = 1;
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input CLK1;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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output [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_A-1:0] A1EN, B1EN;
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altsyncram #(
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.operation_mode("dual_port"),
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.ram_block_type("m20k"),
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.widthad_a(CFG_ABITS),
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.width_a(CFG_DBITS),
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.widthad_b(CFG_ABITS),
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.width_b(CFG_DBITS),
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) _TECHMAP_REPLACE_ (
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.address_a(A1ADDR),
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.data_a(A1DATA),
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.wren_a(A1EN),
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.address_b(B1ADDR),
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.q_b(B1DATA),
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.clock0(CLK1),
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.clock1(CLK1)
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);
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endmodule
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@ -1,21 +1,20 @@
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bram MISTRAL_M10K
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bram MISTRAL_M9K
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init 0 # TODO: Re-enable when I figure out how BRAM init works
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abits 13 @D8192x1
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dbits 1 @D8192x1
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abits 12 @D4096x2
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dbits 2 @D4096x2
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abits 11 @D2048x4 @D2048x5
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abits 11 @D2048x4
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dbits 4 @D2048x4
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dbits 5 @D2048x5
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abits 10 @D1024x8 @D1024x10
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abits 10 @D1024x8 @D1024x9
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dbits 8 @D1024x8
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dbits 10 @D1024x10
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abits 9 @D512x16 @D512x20
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dbits 9 @D1024x9
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abits 9 @D512x16 @D512x18
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dbits 16 @D512x16
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dbits 20 @D512x20
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abits 8 @D256x32 @D256x40
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dbits 18 @D512x18
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abits 8 @D256x32 @D256x36
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dbits 32 @D256x32
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dbits 40 @D256x40
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dbits 36 @D256x36
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groups 2
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ports 1 1
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wrmode 1 0
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@ -1,51 +0,0 @@
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`default_nettype none
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module __MUL27X27(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 27;
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parameter B_WIDTH = 27;
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parameter Y_WIDTH = 54;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL27X27 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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module __MUL18X18(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL18X18 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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module __MUL9X9(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL9X9 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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@ -1,83 +0,0 @@
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(* abc9_box *)
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module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 3732;
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(B *> Y) = 3928;
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endspecify
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wire [53:0] A_, B_;
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if (A_SIGNED)
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assign A_ = $signed(A);
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else
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assign A_ = $unsigned(A);
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if (B_SIGNED)
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assign B_ = $signed(B);
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else
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assign B_ = $unsigned(B);
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assign Y = A_ * B_;
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 3180;
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(B *> Y) = 3982;
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endspecify
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wire [35:0] A_, B_;
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if (A_SIGNED)
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assign A_ = $signed(A);
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else
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assign A_ = $unsigned(A);
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if (B_SIGNED)
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assign B_ = $signed(B);
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else
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assign B_ = $unsigned(B);
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assign Y = A_ * B_;
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 2818;
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(B *> Y) = 3051;
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endspecify
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wire [17:0] A_, B_;
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if (A_SIGNED)
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assign A_ = $signed(A);
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else
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assign A_ = $unsigned(A);
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if (B_SIGNED)
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assign B_ = $signed(B);
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else
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assign B_ = $unsigned(B);
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assign Y = A_ * B_;
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endmodule
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@ -231,32 +231,30 @@ assign Q = ~A;
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endmodule
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(* abc9_box, lib_whitebox *)
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module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output , (* abc9_carry *) output CO);
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module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
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parameter LUT = 16'h0000;
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parameter sum_lutc_input = "cin";
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`ifdef cycloneiv
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`ifdef cycloneiv
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specify
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(A => SO) = 1342;
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(B => SO) = 1323;
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(C => SO) = 927;
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(D0 => SO) = 887;
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(D1 => SO) = 785;
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(D => SO) = 887;
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(CI => SO) = 368;
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(A => CO) = 1082;
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(B => CO) = 1062;
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(C => CO) = 813;
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(D0 => CO) = 866;
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(D1 => CO) = 1198;
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(D => CO) = 866;
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(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
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endspecify
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`endif
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wire q0, q1;
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assign q0 = LUT0 >> sum_lutc_input == "cin" : {D, CI, B, A},{D, C, B, A};
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assign q1 = LUT0 >> sum_lutc_input == "cin" : {'b0, CI, B, A},{'b0, C, B, A};
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assign q0 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A};
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assign q1 = LUT >> sum_lutc_input == "cin" ? {'b1, CI, B, A}:{'b1, C, B, A};
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assign SO = D ? q1 : q0;
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@ -74,7 +74,7 @@ assign B1DATA = mem[B1ADDR];
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endmodule
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// The M10K
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// The M9K
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// --------
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// TODO
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@ -3,11 +3,6 @@
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`define MAC cycloneiv_mac
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`define MLAB cycloneiv_mlab_cell
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`endif
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`ifdef cyclone10gx
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`define LCELL cyclone10gx_lcell_comb
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`define MAC cyclone10gx_mac
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`define MLAB cyclone10gx_mlab_cell
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`endif
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module __MISTRAL_VCC(output Q);
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@ -30,20 +25,6 @@ dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .
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endmodule
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module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
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parameter [63:0] LUT = 64'h0000_0000_0000_0000;
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`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
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endmodule
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module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
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parameter [31:0] LUT = 32'h0000_0000;
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`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
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endmodule
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module MISTRAL_ALUT4(input A, B, C, D, output Q);
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@ -77,11 +58,10 @@ NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
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endmodule
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module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
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parameter LUT0 = 16'h0000;
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parameter LUT1 = 16'h0000;
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module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO);
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parameter LUT = 16'h0000;
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`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
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`LCELL #(.lut_mask({16'h0, LUT})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .sumout(SO), .cout(CO));
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endmodule
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@ -125,7 +105,7 @@ parameter _TECHMAP_CELLNAME_ = "";
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endmodule
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module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
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module MISTRAL_M9K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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@ -137,7 +117,7 @@ input [CFG_DBITS-1:0] A1DATA;
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input CLK1, A1EN, B1EN;
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output [CFG_DBITS-1:0] B1DATA;
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// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
|
||||
// Much like the MLAB, the M9K has mem_init[01234] parameters which would let
|
||||
// you initialise the RAM cell via hex literals. If they were implemented.
|
||||
|
||||
cycloneiv_ram_block #(
|
||||
|
|
@ -172,64 +152,3 @@ cycloneiv_ram_block #(
|
|||
endmodule
|
||||
|
||||
|
||||
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
|
||||
|
||||
parameter A_SIGNED = 1;
|
||||
parameter B_SIGNED = 1;
|
||||
|
||||
`MAC #(
|
||||
.ax_width(27),
|
||||
.signed_max(A_SIGNED ? "true" : "false"),
|
||||
.ay_scan_in_width(27),
|
||||
.signed_may(B_SIGNED ? "true" : "false"),
|
||||
.result_a_width(54),
|
||||
.operation_mode("M27x27")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ax(A),
|
||||
.ay(B),
|
||||
.resulta(Y)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
|
||||
|
||||
parameter A_SIGNED = 1;
|
||||
parameter B_SIGNED = 1;
|
||||
|
||||
`MAC #(
|
||||
.ax_width(18),
|
||||
.signed_max(A_SIGNED ? "true" : "false"),
|
||||
.ay_scan_in_width(18),
|
||||
.signed_may(B_SIGNED ? "true" : "false"),
|
||||
.result_a_width(36),
|
||||
.operation_mode("M18x18_FULL")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ax(A),
|
||||
.ay(B),
|
||||
.resulta(Y)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
|
||||
|
||||
parameter A_SIGNED = 1;
|
||||
parameter B_SIGNED = 1;
|
||||
|
||||
`MAC #(
|
||||
.ax_width(9),
|
||||
.signed_max(A_SIGNED ? "true" : "false"),
|
||||
.ay_scan_in_width(9),
|
||||
.signed_may(B_SIGNED ? "true" : "false"),
|
||||
.result_a_width(18),
|
||||
.operation_mode("M9x9")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ax(A),
|
||||
.ay(B),
|
||||
.resulta(Y)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/*
|
||||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
|
|
@ -41,22 +41,23 @@ endmodule // cycloneiv_io_obuf
|
|||
/* Altera Cyclone IV LUT Primitive */
|
||||
module cycloneiv_lcell_comb
|
||||
(output combout, cout,
|
||||
input dataa, datab, datac, datad,
|
||||
input datae, dataf, datag, cin);
|
||||
input dataa, datab, datac, datad, cin);
|
||||
|
||||
parameter lut_mask = 16'hFFFF;
|
||||
parameter dont_touch = "off";
|
||||
parameter lpm_type = "cycloneiv_lcell_comb";
|
||||
|
||||
parameter sum_lutc_input = "datac";
|
||||
|
||||
// Internal variables
|
||||
reg cout_tmp;
|
||||
reg combout_tmp;
|
||||
|
||||
reg [1:0] isum_lutc_input;
|
||||
|
||||
// Independent output for fragmented LUTs
|
||||
wire output_0, output_1, output_2, output_3;
|
||||
// Extended mode uses mux to define the output
|
||||
wire mux_0, mux_1;
|
||||
// Input for hold the shared LUT mode value
|
||||
wire shared_lut_alm;
|
||||
wire dataa_in;
|
||||
wire datab_in;
|
||||
wire datac_in;
|
||||
wire datad_in;
|
||||
wire cin_in;
|
||||
|
||||
// Simulation model of 4-input LUT
|
||||
function lut4;
|
||||
|
|
@ -73,35 +74,41 @@ module cycloneiv_lcell_comb
|
|||
end
|
||||
endfunction // lut4
|
||||
|
||||
// Simulation model of 5-input LUT
|
||||
function lut5;
|
||||
input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
|
||||
input dataa, datab, datac, datad, datae;
|
||||
reg upper_lut_value;
|
||||
reg lower_lut_value;
|
||||
begin
|
||||
upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
|
||||
lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
|
||||
lut5 = (datae) ? upper_lut_value : lower_lut_value;
|
||||
end
|
||||
endfunction // lut5
|
||||
|
||||
// Simulation model of 6-input LUT
|
||||
function lut6;
|
||||
input [63:0] mask;
|
||||
input dataa, datab, datac, datad, datae, dataf;
|
||||
reg upper_lut_value;
|
||||
reg lower_lut_value;
|
||||
reg out_0, out_1, out_2, out_3;
|
||||
begin
|
||||
upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
|
||||
lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
|
||||
lut6 = (dataf) ? upper_lut_value : lower_lut_value;
|
||||
end
|
||||
endfunction // lut6
|
||||
initial
|
||||
begin
|
||||
if (sum_lutc_input == "datac")
|
||||
isum_lutc_input = 0;
|
||||
else if (sum_lutc_input == "cin")
|
||||
isum_lutc_input = 1;
|
||||
else
|
||||
begin
|
||||
$display ("Error: Invalid sum_lutc_input specified\n");
|
||||
$display ("Time: %0t Instance: %m", $time);
|
||||
isum_lutc_input = 2;
|
||||
end
|
||||
|
||||
assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
|
||||
end
|
||||
|
||||
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
|
||||
begin
|
||||
|
||||
if (isum_lutc_input == 0) // datac
|
||||
begin
|
||||
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
|
||||
datac_in, datad_in);
|
||||
end
|
||||
else if (isum_lutc_input == 1) // cin
|
||||
begin
|
||||
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
|
||||
cin_in, datad_in);
|
||||
end
|
||||
|
||||
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
|
||||
end
|
||||
|
||||
and (combout, combout_tmp, 1'b1) ;
|
||||
and (cout, cout_tmp, 1'b1) ;
|
||||
endmodule // cycloneiv_lcell_comb
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue