diff --git a/techlibs/intel_le/common/arith_le_map.v b/techlibs/intel_le/common/arith_le_map.v
index b6135975d..75e085520 100644
--- a/techlibs/intel_le/common/arith_le_map.v
+++ b/techlibs/intel_le/common/arith_le_map.v
@@ -40,7 +40,7 @@ generate
     end else begin
         MISTRAL_ALUT_ARITH #(
             .LUT(16'b1010_1010_1010_1010), // Q = A
-        ) alm_start (
+        ) le_start (
             .A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
             .CI(1'b0),
             .SO(),
@@ -52,20 +52,25 @@ endgenerate
 // Carry chain
 genvar i;
 generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-    // TODO: mwk suggests that a pass could merge pre-adder logic into this.
+    
     MISTRAL_ALUT_ARITH #(
         .LUT(16'b0110_0110_0110_0110) // Q = A ? ~B : B
-    ) alm_i (
+    ) le_not_i (
         .A(BI), .B(BX[i]), .C(1'b0), .D(1'b0),
         .CI(1'b0),
         .SO(BTOADDER[i]),
         .CO()
     );
+    
+
+
+	
+		
     MISTRAL_ALUT_ARITH #(
-    		.LUT(16'b1010_1010_1010_1010), // SUM = A xor B xor CI
+    		.LUT(16'b1001_0110_1110_1000), // SUM = A xor B xor CI
     		// CARRYi+1 = A and B or A and CI or B and CI 
-    		.sum_lutc_input("cin")
-    	) alm_start (
+    		//.sum_lutc_input("cin")
+    	) le_i (
     		.A(AA[i]), .B(BTOADDER[i]), .C(1'b1), .D(1'b1),
     		.CI(LE_CARRY[i]),
     		.SO(Y[i]),
diff --git a/techlibs/intel_le/common/le_sim.v b/techlibs/intel_le/common/le_sim.v
index bd1a5ae8e..8fbcdf2a7 100644
--- a/techlibs/intel_le/common/le_sim.v
+++ b/techlibs/intel_le/common/le_sim.v
@@ -234,7 +234,7 @@ endmodule
 module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
 
 parameter LUT = 16'h0000;
-parameter sum_lutc_input = "cin";
+//parameter sum_lutc_input = "cin";
 `ifdef cycloneiv 
 specify
     (A  => SO) = 1342;
@@ -253,10 +253,13 @@ endspecify
 
 wire q0, q1;
 
-assign q0 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A};
-assign q1 = LUT >> sum_lutc_input == "cin" ? {'b1, CI, B, A}:{'b1, C, B, A};
+//assign q0 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A};
+//assign q1 = LUT >> sum_lutc_input == "cin" ? {'b0, CI, B, A}:{'b0, C, B, A};
 
-assign SO = D ? q1 : q0;
+assign q0 = LUT >> {'b0, CI, B, A};
+assign q1 = LUT >> {D, CI, B, A};
+
+assign SO = q1;
 
 assign CO = q0;
 
diff --git a/techlibs/intel_le/synth_intel_le.cc b/techlibs/intel_le/synth_intel_le.cc
index 910eed4ad..84527fab1 100644
--- a/techlibs/intel_le/synth_intel_le.cc
+++ b/techlibs/intel_le/synth_intel_le.cc
@@ -170,7 +170,6 @@ struct SynthIntelLEPass : public ScriptPass {
 				run(stringf("read_verilog -sv -lib +/intel_le/%s/cells_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/le_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dff_sim.v", family_opt.c_str()));
-			run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dsp_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/mem_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s -icells +/intel_le/common/abc9_model.v", family_opt.c_str()));
 
@@ -196,11 +195,11 @@ struct SynthIntelLEPass : public ScriptPass {
 			run("peepopt");
 			run("opt_clean");
 			run("share");
-			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
 			run("opt_clean");
 			run("alumacc");
-			run("techmap -map +/intel_le/common/arith_le_map.v -map +/intel_le/common/dsp_map.v");
+			run("techmap -map +/intel_le/common/arith_le_map.v");
 			run("opt");
 			run("memory -nomap");
 			run("opt_clean");
@@ -227,7 +226,7 @@ struct SynthIntelLEPass : public ScriptPass {
 
 		if (check_label("map_luts")) {
 			run("techmap -map +/intel_le/common/abc9_map.v");
-			run(stringf("abc9 %s -maxlut 6 -W 600", help_mode ? "[-dff]" : dff ? "-dff" : ""));
+			run(stringf("abc9 %s -maxlut 4 -W 400", help_mode ? "[-dff]" : dff ? "-dff" : ""));
 			run("techmap -map +/intel_le/common/abc9_unmap.v");
 			run("techmap -map +/intel_le/common/le_map.v");
 			run("opt -fast");