mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

tiny fix

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-06-13 21:37:22 +02:00
parent 866b7a7121
commit 4c9f68216a
8 changed files with 10 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/connwrappers.cc
View file

@ -105,7 +105,7 @@ struct ConnwrappersWorker
for (auto cell : module->selected_cells())
{
for (auto &&conn : cell->connections_)
for (auto conn : cell->connections_)
{
std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
RTLIL::SigSpec old_sig;

2
passes/cmds/splice.cc
View file

@ -188,7 +188,7 @@ struct SpliceWorker
for (auto cell : mod_cells) {
if (!sel_by_wire && !design->selected(module, cell))
continue;
for (auto &&conn : cell->connections_)
for (auto conn : cell->connections_)
if (ct.cell_input(cell->type, conn.first)) {
if (ports.size() > 0 && !ports.count(conn.first))
continue;

2
passes/hierarchy/hierarchy.cc
View file

@ -575,7 +575,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
RTLIL::Module *mod = design->module(cell->type);
for (auto &&conn : cell->connections_) {
for (auto conn : cell->connections_) {
int conn_size = conn.second.size();
RTLIL::IdString portname = conn.first;
if (portname.begins_with("$")) {

2
passes/opt/opt_clean.cc
View file

@ -361,7 +361,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
// gather the usage information for cells
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
for (auto &it2 : cell->connections_) {
for (auto it2 : cell->connections_) {
assign_map.apply(it2.second); // modify the cell connection in place
raw_used_signals.add(it2.second);
used_signals.add(it2.second);

4
passes/sat/expose.cc
View file

@ -498,7 +498,7 @@ struct ExposePass : public Pass {
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
for (auto &&conn : cell->connections_)
for (auto conn : cell->connections_)
if (ct.cell_output(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@ -519,7 +519,7 @@ struct ExposePass : public Pass {
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
for (auto &&conn : cell->connections_)
for (auto conn : cell->connections_)
if (ct.cell_input(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}