From 4c9f68216a742dc0ac5983e3a74197dcc1ba884c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 13 Jun 2024 21:37:22 +0200 Subject: [PATCH] tiny fix --- kernel/ffmerge.cc | 2 +- kernel/rtlil.cc | 2 +- kernel/rtlil.h | 4 ++-- passes/cmds/connwrappers.cc | 2 +- passes/cmds/splice.cc | 2 +- passes/hierarchy/hierarchy.cc | 2 +- passes/opt/opt_clean.cc | 2 +- passes/sat/expose.cc | 4 ++-- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index cecc6a835..2c4e2906c 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -345,7 +345,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_) for (int i = 0; i < GetSize(q); i++) dff_driver[q[i]] = std::make_pair(cell, i); } - for (auto &&conn : cell->connections_) + for (auto conn : cell->connections_) if (!cell->known() || cell->input(conn.first)) for (auto bit : (*sigmap)(conn.second)) sigbit_users_count[bit]++; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6f40bdd66..70b63109d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1090,7 +1090,7 @@ namespace { for (auto &¶ : cell->parameters) if (expected_params.count(para.first) == 0) error(__LINE__); - for (auto &&conn : cell->connections_) + for (auto conn : cell->connections_) if (expected_ports.count(conn.first) == 0) error(__LINE__); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 03a640133..833bd3b54 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1691,7 +1691,7 @@ public: return parent->getParam(name); } void sort() {} - void reserve() {} + void reserve(int n) { (void)n; } // Watch out! This is different semantics than what dict has! // but we rely on RTLIL::Cell always being constructed correctly // since its layout is fixed as defined by InternalOldCellChecker @@ -1903,7 +1903,7 @@ public: return parent->getPort(name); } void sort() {} - void reserve() {} + void reserve(int n) { (void)n; } // Watch out! This is different semantics than what dict has! // but we rely on RTLIL::Cell always being constructed correctly // since its layout is fixed as defined by InternalOldCellChecker diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 436b5dba7..9bf7c03ab 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -105,7 +105,7 @@ struct ConnwrappersWorker for (auto cell : module->selected_cells()) { - for (auto &&conn : cell->connections_) + for (auto conn : cell->connections_) { std::vector sigbits = sigmap(conn.second).to_sigbit_vector(); RTLIL::SigSpec old_sig; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 2cbddd392..3984085fe 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -188,7 +188,7 @@ struct SpliceWorker for (auto cell : mod_cells) { if (!sel_by_wire && !design->selected(module, cell)) continue; - for (auto &&conn : cell->connections_) + for (auto conn : cell->connections_) if (ct.cell_input(cell->type, conn.first)) { if (ports.size() > 0 && !ports.count(conn.first)) continue; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 69382dc17..a6b8da2eb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -575,7 +575,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check RTLIL::Module *mod = design->module(cell->type); - for (auto &&conn : cell->connections_) { + for (auto conn : cell->connections_) { int conn_size = conn.second.size(); RTLIL::IdString portname = conn.first; if (portname.begins_with("$")) { diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index b6933eb0f..a4945235f 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -361,7 +361,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos // gather the usage information for cells for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections_) { + for (auto it2 : cell->connections_) { assign_map.apply(it2.second); // modify the cell connection in place raw_used_signals.add(it2.second); used_signals.add(it2.second); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 8e9c76164..d367ec93c 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -498,7 +498,7 @@ struct ExposePass : public Pass { for (auto cell : module->cells()) { if (!ct.cell_known(cell->type)) continue; - for (auto &&conn : cell->connections_) + for (auto conn : cell->connections_) if (ct.cell_output(cell->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); } @@ -519,7 +519,7 @@ struct ExposePass : public Pass { for (auto cell : module->cells()) { if (!ct.cell_known(cell->type)) continue; - for (auto &&conn : cell->connections_) + for (auto conn : cell->connections_) if (ct.cell_input(cell->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); }