diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt index 7bcbeb0a8..209f232c7 100644 --- a/techlibs/analogdevices/brams.txt +++ b/techlibs/analogdevices/brams.txt @@ -1,165 +1,39 @@ -# Block RAMs for Virtex 4+. -# The corresponding mapping files are: -# - brams_xc6v_map.v: Virtex 6, Series 7 +# Simple Dual Port +# Supported: +# SDP_4096x05 +# SDP_2048x10 +# SDP_1024x40 +# Ignored: +# SDP_2048x09 -ram block $__ANALOGDEVICES_BLOCKRAM_TDP_ { - byte 9; - ifdef HAS_SIZE_36 { - option "MODE" "HALF" { - abits 14; - widths 1 2 4 9 18 per_port; - cost 129; - } - option "MODE" "FULL" { - abits 15; - widths 1 2 4 9 18 36 per_port; - cost 257; - } - ifdef HAS_CASCADE { - option "MODE" "CASCADE" { - abits 16; - # hack to enforce same INIT layout as in the other modes - widths 1 2 4 9 per_port; - cost 513; - } - } - } else { - option "MODE" "FULL" { - abits 14; - widths 1 2 4 9 18 36 per_port; - cost 129; - } - ifdef HAS_CASCADE { - option "MODE" "CASCADE" { - abits 15; - widths 1 2 4 9 per_port; - cost 257; - } - } +ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { + option "ENABLE_WIDTH" "BIT" { + abits 12; + widths 5 10 global; + byte 1; + cost 1; } - init any; - port srsw "A" "B" { - option "MODE" "HALF" { - width mix; - } - option "MODE" "FULL" { - width mix; - } - option "MODE" "CASCADE" { - width mix 1; - } - ifdef HAS_ADDRCE { - # TODO - # addrce; - } - # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. - ifdef HAS_CONFLICT_BUG { - option "HAS_RDFIRST" 1 { - clock posedge "C"; - } - option "HAS_RDFIRST" 0 { - clock posedge; - } - } else { - clock posedge; - } + option "ENABLE_WIDTH" "BYTE" { + abits 10; + width 40; + byte 8; + cost 4; + } + # Unclear if/how RBRAM is initialized, default SIM_INIT_BEHAVIOUR is UNINITIALIZED + init none; + port sr "R" { + clock anyedge; + clken; + } + port sw "W" { + clock anyedge; clken; - rdsrst any gated_clken; - rdinit any; - portoption "WRITE_MODE" "NO_CHANGE" { - rdwr no_change; - option "MODE" "CASCADE" { - forbid; - } - } - portoption "WRITE_MODE" "WRITE_FIRST" { - ifdef HAS_SIZE_36 { - rdwr new; - } else { - rdwr new_only; - } - } - ifdef HAS_CONFLICT_BUG { - option "HAS_RDFIRST" 1 { - portoption "WRITE_MODE" "READ_FIRST" { - rdwr old; - wrtrans all old; - } - } - } else { - portoption "WRITE_MODE" "READ_FIRST" { - rdwr old; - wrtrans all old; - } - } - optional_rw; } } -ifdef HAS_SIZE_36 { - ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ { - byte 9; - option "MODE" "HALF" { - abits 14; - widths 1 2 4 9 18 36 per_port; - cost 129; - } - option "MODE" "FULL" { - abits 15; - widths 1 2 4 9 18 36 72 per_port; - cost 257; - } - init any; - port sw "W" { - ifndef HAS_MIXWIDTH_SDP { - option "MODE" "HALF" width 36; - option "MODE" "FULL" width 72; - } - ifdef HAS_ADDRCE { - # TODO - # addrce; - } - # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. - ifdef HAS_CONFLICT_BUG { - option "WRITE_MODE" "READ_FIRST" { - clock posedge "C"; - } - option "WRITE_MODE" "WRITE_FIRST" { - clock posedge; - } - } else { - clock posedge; - } - clken; - option "WRITE_MODE" "READ_FIRST" { - wrtrans all old; - } - optional; - } - port sr "R" { - ifndef HAS_MIXWIDTH_SDP { - option "MODE" "HALF" width 36; - option "MODE" "FULL" width 72; - } - ifdef HAS_ADDRCE { - # TODO - # addrce; - } - # Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks. - ifdef HAS_CONFLICT_BUG { - option "WRITE_MODE" "READ_FIRST" { - clock posedge "C"; - } - option "WRITE_MODE" "WRITE_FIRST" { - clock posedge; - } - } else { - clock posedge; - } - clken; - rdsrst any gated_clken; - rdinit any; - optional; - } - } -} +# Single Port +# SP_1024x20 + +# Dual Single Port +# SP2_1024x09 +# SP2_2048x05 diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v index f4655a220..6d590501e 100644 --- a/techlibs/analogdevices/brams_map.v +++ b/techlibs/analogdevices/brams_map.v @@ -1,284 +1,64 @@ -module $__ANALOGDEVICES_BLOCKRAM_TDP_ (...); - -parameter INIT = 0; -parameter OPTION_MODE = "FULL"; -parameter OPTION_HAS_RDFIRST = 0; - -parameter PORT_A_RD_WIDTH = 1; -parameter PORT_A_WR_WIDTH = 1; -parameter PORT_A_WR_EN_WIDTH = 1; -parameter PORT_A_RD_USED = 1; -parameter PORT_A_WR_USED = 1; -parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE"; -parameter PORT_A_RD_INIT_VALUE = 0; -parameter PORT_A_RD_SRST_VALUE = 1; - -parameter PORT_B_RD_WIDTH = 1; -parameter PORT_B_WR_WIDTH = 1; -parameter PORT_B_WR_EN_WIDTH = 1; -parameter PORT_B_RD_USED = 0; -parameter PORT_B_WR_USED = 0; -parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE"; -parameter PORT_B_RD_INIT_VALUE = 0; -parameter PORT_B_RD_SRST_VALUE = 0; - -input CLK_C; - -input PORT_A_CLK; -input PORT_A_CLK_EN; -input [15:0] PORT_A_ADDR; -input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA; -input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN; -output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA; -input PORT_A_RD_SRST; - -input PORT_B_CLK; -input PORT_B_CLK_EN; -input [15:0] PORT_B_ADDR; -input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA; -input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN; -output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA; -input PORT_B_RD_SRST; - -`include "brams_defs.vh" - -`define PARAMS_COMMON \ - .WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \ - .WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \ - .READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \ - .READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \ - .WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \ - .WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \ - .DOA_REG(0), \ - .DOB_REG(0), \ - .INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \ - .INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \ - .SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \ - .SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)), \ - .RAM_MODE("TDP"), - -`define PORTS_COMMON \ - .DOADO(DO_A), \ - .DOPADOP(DOP_A), \ - .DIADI(DI_A), \ - .DIPADIP(DIP_A), \ - .DOBDO(DO_B), \ - .DOPBDOP(DOP_B), \ - .DIBDI(DI_B), \ - .DIPBDIP(DIP_B), \ - .CLKARDCLK(PORT_A_CLK), \ - .CLKBWRCLK(PORT_B_CLK), \ - .ENARDEN(PORT_A_CLK_EN), \ - .ENBWREN(PORT_B_CLK_EN), \ - .REGCEAREGCE(1'b0), \ - .REGCEB(1'b0), \ - .RSTRAMARSTRAM(PORT_A_RD_SRST), \ - .RSTRAMB(PORT_B_RD_SRST), \ - .RSTREGARSTREG(1'b0), \ - .RSTREGB(1'b0), \ - .WEA(WE_A), \ - .WEBWE(WE_B), - -`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA) -`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA) -`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA) -`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA) - -wire [3:0] WE_A = {4{PORT_A_WR_EN}}; -wire [3:0] WE_B = {4{PORT_B_WR_EN}}; - -generate - -if (OPTION_MODE == "HALF") begin - RAMB18E1 #( - `PARAMS_INIT_18 - `PARAMS_INITP_18 - `PARAMS_COMMON - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR(PORT_A_ADDR[13:0]), - .ADDRBWRADDR(PORT_B_ADDR[13:0]), - ); -end else if (OPTION_MODE == "FULL") begin - RAMB36E1 #( - `PARAMS_INIT_36 - `PARAMS_INITP_36 - `PARAMS_COMMON - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR({1'b1, PORT_A_ADDR[14:0]}), - .ADDRBWRADDR({1'b1, PORT_B_ADDR[14:0]}), - ); -end else begin - wire CAS_A, CAS_B; - RAMB36E1 #( - `PARAMS_INIT_36 - `PARAMS_COMMON - .RAM_EXTENSION_A("LOWER"), - .RAM_EXTENSION_B("LOWER"), - ) lower ( - .DIADI(DI_A), - .DIBDI(DI_B), - .CLKARDCLK(PORT_A_CLK), - .CLKBWRCLK(PORT_B_CLK), - .ENARDEN(PORT_A_CLK_EN), - .ENBWREN(PORT_B_CLK_EN), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(PORT_A_RD_SRST), - .RSTRAMB(PORT_B_RD_SRST), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .WEA(WE_A), - .WEBWE(WE_B), - .ADDRARDADDR(PORT_A_ADDR), - .ADDRBWRADDR(PORT_B_ADDR), - .CASCADEOUTA(CAS_A), - .CASCADEOUTB(CAS_B), - ); - RAMB36E1 #( - `PARAMS_INIT_36_U - `PARAMS_COMMON - .RAM_EXTENSION_A("UPPER"), - .RAM_EXTENSION_B("UPPER"), - ) upper ( - .DOADO(DO_A), - .DIADI(DI_A), - .DOBDO(DO_B), - .DIBDI(DI_B), - .CLKARDCLK(PORT_A_CLK), - .CLKBWRCLK(PORT_B_CLK), - .ENARDEN(PORT_A_CLK_EN), - .ENBWREN(PORT_B_CLK_EN), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(PORT_A_RD_SRST), - .RSTRAMB(PORT_B_RD_SRST), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .WEA(WE_A), - .WEBWE(WE_B), - .ADDRARDADDR(PORT_A_ADDR), - .ADDRBWRADDR(PORT_B_ADDR), - .CASCADEINA(CAS_A), - .CASCADEINB(CAS_B), - ); -end - -endgenerate - -endmodule - - module $__ANALOGDEVICES_BLOCKRAM_SDP_ (...); parameter INIT = 0; -parameter OPTION_MODE = "FULL"; -parameter OPTION_WRITE_MODE = "READ_FIRST"; +parameter OPTION_ENABLE_WIDTH = "BIT"; +parameter WIDTH = 40; -parameter PORT_W_WIDTH = 1; -parameter PORT_W_WR_EN_WIDTH = 1; -parameter PORT_W_USED = 1; +parameter PORT_W_WR_EN_WIDTH = 5; +parameter PORT_W_CLK_POL = 1; -parameter PORT_R_WIDTH = 1; -parameter PORT_R_USED = 0; -parameter PORT_R_RD_INIT_VALUE = 0; -parameter PORT_R_RD_SRST_VALUE = 0; - -input CLK_C; +parameter PORT_R_CLK_POL = 1; input PORT_W_CLK; input PORT_W_CLK_EN; -input [15:0] PORT_W_ADDR; -input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; +input [11:0] PORT_W_ADDR; +input [WIDTH-1:0] PORT_W_WR_DATA; input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; input PORT_R_CLK; input PORT_R_CLK_EN; -input [15:0] PORT_R_ADDR; -output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; -input PORT_R_RD_SRST; +input [11:0] PORT_R_ADDR; +output [WIDTH-1:0] PORT_R_RD_DATA; -`include "brams_defs.vh" - -`define PARAMS_COMMON \ - .WRITE_MODE_A(OPTION_WRITE_MODE), \ - .WRITE_MODE_B(OPTION_WRITE_MODE), \ - .READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \ - .READ_WIDTH_B(0), \ - .WRITE_WIDTH_A(0), \ - .WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \ - .DOA_REG(0), \ - .DOB_REG(0), \ - .RAM_MODE("SDP"), - -`define PORTS_COMMON \ - .CLKBWRCLK(PORT_W_CLK), \ - .CLKARDCLK(PORT_R_CLK), \ - .ENBWREN(PORT_W_CLK_EN), \ - .ENARDEN(PORT_R_CLK_EN), \ - .REGCEAREGCE(1'b0), \ - .REGCEB(1'b0), \ - .RSTRAMARSTRAM(PORT_R_RD_SRST), \ - .RSTRAMB(1'b0), \ - .RSTREGARSTREG(1'b0), \ - .RSTREGB(1'b0), \ - .WEA(0), \ - .WEBWE(PORT_W_WR_EN), - -`MAKE_DI(DI, DIP, PORT_W_WR_DATA) -`MAKE_DO(DO, DOP, PORT_R_RD_DATA) - -generate - -if (OPTION_MODE == "HALF") begin - RAMB18E1 #( - `PARAMS_INIT_18 - `PARAMS_INITP_18 - `PARAMS_COMMON - .INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)), - .INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0), - .SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)), - .SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0), - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR(PORT_R_ADDR[13:0]), - .ADDRBWRADDR(PORT_W_ADDR[13:0]), - .DOADO(DO[15:0]), - .DOBDO(DO[31:16]), - .DOPADOP(DOP[1:0]), - .DOPBDOP(DOP[3:2]), - .DIADI(DI[15:0]), - .DIBDI(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]), - .DIPADIP(DIP[1:0]), - .DIPBDIP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]), - ); -end else if (OPTION_MODE == "FULL") begin - RAMB36E1 #( - `PARAMS_INIT_36 - `PARAMS_INITP_36 - `PARAMS_COMMON - .INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)), - .INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0), - .SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)), - .SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0), - ) _TECHMAP_REPLACE_ ( - `PORTS_COMMON - .ADDRARDADDR({1'b1, PORT_R_ADDR}), - .ADDRBWRADDR({1'b1, PORT_W_ADDR}), - .DOADO(DO[31:0]), - .DOBDO(DO[63:32]), - .DOPADOP(DOP[3:0]), - .DOPBDOP(DOP[7:4]), - .DIADI(DI[31:0]), - .DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]), - .DIPADIP(DIP[3:0]), - .DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]), - ); -end - -endgenerate +RBRAM +#( + .TARGET_NODE("T40LP_Gen2.4"), + .BRAM_MODE( + WIDTH == 5 ? "SDP_4096x05" : + WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40" + ), + .QA_REG(0), + .QB_REG(0), + .CLKA_INV(!PORT_W_CLK_POL), + .CLKB_INV(!PORT_R_CLK_POL), + .DATA_WIDTH(WIDTH), + .ADDR_WIDTH( + WIDTH == 5 ? 12 : + WIDTH == 10 ? 11 : 10 + ), + .WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH), + .PERR_WIDTH(1), +) +_TECHMAP_REPLACE_ +( + // .QA(0), + .DA(PORT_W_WR_DATA), + .CEA(PORT_W_CLK_EN), + .WEA(PORT_W_WR_EN), + .AA( + WIDTH == 5 ? PORT_W_ADDR : + WIDTH == 10 ? PORT_W_ADDR[11:1] : PORT_W_ADDR[11:2] + ), + .CLKA(PORT_W_CLK), + .QB(PORT_R_RD_DATA), + // .DB(0), + .CEB(PORT_R_CLK_EN), + // .WEB(0), + .AB( + WIDTH == 5 ? PORT_R_ADDR : + WIDTH == 10 ? PORT_R_ADDR[11:1] : PORT_R_ADDR[11:2] + ), + .CLKB(PORT_R_CLK), +); endmodule diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 8dac86f94..66bb10cbe 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -2423,444 +2423,42 @@ endmodule // Block RAM -module RAMB18E1 ( +module RBRAM #( + parameter TARGET_NODE = "T40LP_Gen2.4", + parameter BRAM_MODE = "SDP_1024x40", + parameter QA_REG = 0, + parameter QB_REG = 0, + parameter CLKA_INV = 0, + parameter CLKB_INV = 0, + parameter DATA_WIDTH = 40, + parameter ADDR_WIDTH = 12, + parameter WE_WIDTH = 10, + parameter PERR_WIDTH = 4, +) ( + output [DATA_WIDTH-1:0] QA, + input [DATA_WIDTH-1:0] DA, + input CEA, + input [WE_WIDTH-1:0] WEA, + input [ADDR_WIDTH-1:0] AA, (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK, + (* invertible_pin = "CLKA_INV" *) + input CLKA, + output [DATA_WIDTH-1:0] QB, + input [DATA_WIDTH-1:0] DB, + input CEB, + input [WE_WIDTH-1:0] WEB, + input [ADDR_WIDTH-1:0] AB, (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK, - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN, - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN, - input REGCEAREGCE, - input REGCEB, - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM, - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB, - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG, - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB, - input [13:0] ADDRARDADDR, - input [13:0] ADDRBWRADDR, - input [15:0] DIADI, - input [15:0] DIBDI, - input [1:0] DIPADIP, - input [1:0] DIPBDIP, - input [1:0] WEA, - input [3:0] WEBWE, - output [15:0] DOADO, - output [15:0] DOBDO, - output [1:0] DOPADOP, - output [1:0] DOPBDOP + (* invertible_pin = "CLKB_INV" *) + input CLKB, + output reg [PERR_WIDTH-1:0] PERRA, + output reg [PERR_WIDTH-1:0] PERRB, + output SBEA, + output SBEB, + output MBEA, + output MBEB, + input SLP, + input PD, ); - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_A = 18'h0; - parameter INIT_B = 18'h0; - parameter INIT_FILE = "NONE"; - parameter RAM_MODE = "TDP"; - parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL_A = 18'h0; - parameter SRVAL_B = 18'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13 - $setup(ADDRARDADDR, posedge CLKARDCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17 - $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19 - $setup(WEA, posedge CLKARDCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21 - $setup(WEBWE, posedge CLKBWRCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29 - $setup(REGCEAREGCE, posedge CLKARDCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31 - $setup(RSTREGARSTREG, posedge CLKARDCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49 - $setup(REGCEB, posedge CLKBWRCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59 - $setup(RSTREGB, posedge CLKBWRCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123 - $setup(DIADI, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133 - $setup(DIBDI, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125 - $setup(DIPADIP, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135 - $setup(DIPBDIP, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143 - if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144 - if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153 - if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154 - if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163 - if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164 - if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173 - if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174 - if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 882; - endspecify -endmodule - -module RAMB36E1 ( - output CASCADEOUTA, - output CASCADEOUTB, - output [31:0] DOADO, - output [31:0] DOBDO, - output [3:0] DOPADOP, - output [3:0] DOPBDOP, - output [7:0] ECCPARITY, - output [8:0] RDADDRECC, - output SBITERR, - output DBITERR, - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK, - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM, - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG, - input CASCADEINA, - input REGCEAREGCE, - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK, - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB, - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB, - input CASCADEINB, - input REGCEB, - input INJECTDBITERR, - input INJECTSBITERR, - input [15:0] ADDRARDADDR, - input [15:0] ADDRBWRADDR, - input [31:0] DIADI, - input [31:0] DIBDI, - input [3:0] DIPADIP, - input [3:0] DIPBDIP, - input [3:0] WEA, - input [7:0] WEBWE -); - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_A = 36'h0; - parameter INIT_B = 36'h0; - parameter INIT_FILE = "NONE"; - parameter RAM_EXTENSION_A = "NONE"; - parameter RAM_EXTENSION_B = "NONE"; - parameter RAM_MODE = "TDP"; - parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL_A = 36'h0; - parameter SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - - specify - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13 - $setup(ADDRARDADDR, posedge CLKARDCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17 - $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19 - $setup(WEA, posedge CLKARDCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21 - $setup(WEBWE, posedge CLKBWRCLK, 532); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29 - $setup(REGCEAREGCE, posedge CLKARDCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31 - $setup(RSTREGARSTREG, posedge CLKARDCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49 - $setup(REGCEB, posedge CLKBWRCLK, 360); - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59 - $setup(RSTREGB, posedge CLKBWRCLK, 342); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123 - $setup(DIADI, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133 - $setup(DIBDI, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125 - $setup(DIPADIP, posedge CLKARDCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135 - $setup(DIPBDIP, posedge CLKBWRCLK, 737); - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143 - if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144 - if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153 - if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154 - if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163 - if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164 - if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 2454; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173 - if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 882; - // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174 - if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882; - endspecify endmodule diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt index 3218024bb..ce71c4f0c 100644 --- a/techlibs/analogdevices/lutrams.txt +++ b/techlibs/analogdevices/lutrams.txt @@ -1,6 +1,3 @@ -# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7. -# The corresponding mapping file is lutrams_xc5v_map.v - # Single-port RAMs. ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v index d12c9ae81..b4411fd64 100644 --- a/techlibs/analogdevices/lutrams_map.v +++ b/techlibs/analogdevices/lutrams_map.v @@ -1,7 +1,3 @@ -// LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7, Ultrascale. -// The definitions are in lutrams_xc5v.txt. - - module $__ANALOGDEVICES_LUTRAM_SP_ (...); parameter INIT = 0; diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 1c183476d..a1ed745ff 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -343,10 +343,6 @@ struct SynthAnalogDevicesPass : public ScriptPass params += " -lib +/analogdevices/lutrams.txt"; lutrams_map = "+/analogdevices/lutrams_map.v"; params += " -lib +/analogdevices/brams.txt"; - params += " -D HAS_SIZE_36"; - params += " -D HAS_CASCADE"; - params += " -D HAS_CONFLICT_BUG"; - params += " -D HAS_MIXWIDTH_SDP"; brams_map = "+/analogdevices/brams_map.v"; if (nolutram) params += " -no-auto-distributed";