Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl

Upstream verific mixed sv vhdl

frontends/verific/verific.cc

@@ -3744,10 +3744,33 @@ struct VerificPass : public Pass {
 			veri_file::DefineMacro("VERIFIC");
 			veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
 
+#ifdef VERIFIC_VHDL_SUPPORT
+			int i;
+			Array *file_names_sv = new Array(POINTER_HASH);
+			FOREACH_ARRAY_ITEM(file_names, i, filename) {
+				std::string filename_str = filename;
+				if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") ||
+						(filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) {
+					vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str());
+					if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) {
+						verific_error_msg.clear();
+						log_cmd_error("Reading VHDL sources failed.\n");
+					}
+				} else {
+					file_names_sv->Insert(strdup(filename));
+				}
+			}
+			if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) {
+				verific_error_msg.clear();
+				log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
+			}
+			delete file_names_sv;
+#else
 			if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {
 				verific_error_msg.clear();
 				log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 			}
+#endif
 
 			delete file_names;
 			verific_import_pending = true;

tests/verific/mixed_flist.flist

@@ -0,0 +1,2 @@
+mixed_flist.sv
+mixed_flist.vhd

tests/verific/mixed_flist.sv

@@ -0,0 +1,4 @@
+module sv_top(input logic a, output logic y);
+	// Instantiates VHDL entity to ensure mixed -f list is required
+	vhdl_mod u_vhdl(.a(a), .y(y));
+endmodule

tests/verific/mixed_flist.vhd

@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_mod is
+	port (
+		a : in std_logic;
+		y : out std_logic
+	);
+end entity vhdl_mod;
+
+architecture rtl of vhdl_mod is
+begin
+	y <= a;
+end architecture rtl;

tests/verific/mixed_flist.ys

@@ -0,0 +1,3 @@
+verific -f -sv mixed_flist.flist
+verific -import sv_top
+select -assert-mod-count 1 sv_top