From f3c87610f51a20feecac94a37535f374fcfcbdca Mon Sep 17 00:00:00 2001 From: nataliakokoromyti Date: Sat, 24 Jan 2026 23:46:45 -0800 Subject: [PATCH 1/7] verific: allow mixed SV/VHDL in -f files --- frontends/verific/verific.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 92df86fd5..67e70d5e7 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3744,10 +3744,28 @@ struct VerificPass : public Pass { veri_file::DefineMacro("VERIFIC"); veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS"); +#ifdef VERIFIC_VHDL_SUPPORT + int i; + FOREACH_ARRAY_ITEM(file_names, i, filename) { + std::string filename_str = filename; + if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || + (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); + if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { + verific_error_msg.clear(); + log_cmd_error("Reading VHDL sources failed.\n"); + } + } else if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + } +#else if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } +#endif delete file_names; verific_import_pending = true; From 188082551abce31bbb5d7d911320d011147545f8 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 03:37:08 -0800 Subject: [PATCH 2/7] verific: only use MFCU when VHDL present --- frontends/verific/verific.cc | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 67e70d5e7..4012708c2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3746,20 +3746,34 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT int i; + Array *file_names_sv = new Array(POINTER_HASH); + bool has_vhdl = false; FOREACH_ARRAY_ITEM(file_names, i, filename) { std::string filename_str = filename; if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { + has_vhdl = true; vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { verific_error_msg.clear(); log_cmd_error("Reading VHDL sources failed.\n"); } - } else if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { - verific_error_msg.clear(); - log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } else { + file_names_sv->Insert(strdup(filename)); } } + if (has_vhdl) { + FOREACH_ARRAY_ITEM(file_names_sv, i, filename) { + if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + } + } else if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + delete file_names_sv; #else if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); From 74c601db0fbd5573620f1344c55e9c61f5e6ccdc Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 03:55:42 -0800 Subject: [PATCH 3/7] tests/verific: add mixed -f list case --- tests/verific/mixed_flist.flist | 2 ++ tests/verific/mixed_flist.sv | 3 +++ tests/verific/mixed_flist.vhd | 14 ++++++++++++++ tests/verific/mixed_flist.ys | 5 +++++ 4 files changed, 24 insertions(+) create mode 100644 tests/verific/mixed_flist.flist create mode 100644 tests/verific/mixed_flist.sv create mode 100644 tests/verific/mixed_flist.vhd create mode 100644 tests/verific/mixed_flist.ys diff --git a/tests/verific/mixed_flist.flist b/tests/verific/mixed_flist.flist new file mode 100644 index 000000000..d4edb8532 --- /dev/null +++ b/tests/verific/mixed_flist.flist @@ -0,0 +1,2 @@ +mixed_flist.sv +mixed_flist.vhd diff --git a/tests/verific/mixed_flist.sv b/tests/verific/mixed_flist.sv new file mode 100644 index 000000000..83c04054f --- /dev/null +++ b/tests/verific/mixed_flist.sv @@ -0,0 +1,3 @@ +module sv_top(input logic a, output logic y); + assign y = a; +endmodule diff --git a/tests/verific/mixed_flist.vhd b/tests/verific/mixed_flist.vhd new file mode 100644 index 000000000..25a10f963 --- /dev/null +++ b/tests/verific/mixed_flist.vhd @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_mod is + port ( + a : in std_logic; + y : out std_logic + ); +end entity vhdl_mod; + +architecture rtl of vhdl_mod is +begin + y <= a; +end architecture rtl; diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys new file mode 100644 index 000000000..4cbdb1e59 --- /dev/null +++ b/tests/verific/mixed_flist.ys @@ -0,0 +1,5 @@ +verific -f -sv mixed_flist.flist +verific -import sv_top +verific -import vhdl_mod +select -assert-mod-count 1 sv_top +select -assert-mod-count 1 vhdl_mod From 8c2ef89732c0e6755b17be949ec8296ad503b509 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 04:13:04 -0800 Subject: [PATCH 4/7] tests/verific: import mixed -f list with -all --- tests/verific/mixed_flist.ys | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys index 4cbdb1e59..2a0af80db 100644 --- a/tests/verific/mixed_flist.ys +++ b/tests/verific/mixed_flist.ys @@ -1,5 +1,4 @@ verific -f -sv mixed_flist.flist -verific -import sv_top -verific -import vhdl_mod +verific -import -all select -assert-mod-count 1 sv_top -select -assert-mod-count 1 vhdl_mod +select -assert-mod-count 2 From 5a64fe2d9161f24dd4fc3d67c09316c415005ff8 Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 04:21:13 -0800 Subject: [PATCH 5/7] tests/verific: assert module count explicitly --- tests/verific/mixed_flist.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys index 2a0af80db..59849a5e5 100644 --- a/tests/verific/mixed_flist.ys +++ b/tests/verific/mixed_flist.ys @@ -1,4 +1,4 @@ verific -f -sv mixed_flist.flist verific -import -all select -assert-mod-count 1 sv_top -select -assert-mod-count 2 +select -assert-mod-count 2 =* From b6c148f84a5f08f73e23c187148261cff9301e4f Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 22:46:10 -0800 Subject: [PATCH 6/7] tests/verific: ensure mixed -f requires VHDL unit --- tests/verific/mixed_flist.sv | 3 ++- tests/verific/mixed_flist.ys | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/verific/mixed_flist.sv b/tests/verific/mixed_flist.sv index 83c04054f..28e073891 100644 --- a/tests/verific/mixed_flist.sv +++ b/tests/verific/mixed_flist.sv @@ -1,3 +1,4 @@ module sv_top(input logic a, output logic y); - assign y = a; + // Instantiates VHDL entity to ensure mixed -f list is required + vhdl_mod u_vhdl(.a(a), .y(y)); endmodule diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys index 59849a5e5..9f5fe607a 100644 --- a/tests/verific/mixed_flist.ys +++ b/tests/verific/mixed_flist.ys @@ -1,4 +1,3 @@ verific -f -sv mixed_flist.flist -verific -import -all +verific -import sv_top select -assert-mod-count 1 sv_top -select -assert-mod-count 2 =* From 8d504ecb48c2338d9f6991ee4e9c0222761ed36a Mon Sep 17 00:00:00 2001 From: Natalia Date: Thu, 29 Jan 2026 00:03:28 -0800 Subject: [PATCH 7/7] verific: use MFCU for SV file list --- frontends/verific/verific.cc | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 4012708c2..299b38d16 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3747,12 +3747,10 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT int i; Array *file_names_sv = new Array(POINTER_HASH); - bool has_vhdl = false; FOREACH_ARRAY_ITEM(file_names, i, filename) { std::string filename_str = filename; if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { - has_vhdl = true; vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { verific_error_msg.clear(); @@ -3762,14 +3760,7 @@ struct VerificPass : public Pass { file_names_sv->Insert(strdup(filename)); } } - if (has_vhdl) { - FOREACH_ARRAY_ITEM(file_names_sv, i, filename) { - if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { - verific_error_msg.clear(); - log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); - } - } - } else if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) { + if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); }