Merge 64d483442f into 22c15a7ecd

tests/proc/proc_latches.ys

@@ -22,6 +22,20 @@ logger -check-expected
 
 design -reset
 
+# always_latch is exempt
+read_verilog -sv <<EOT
+module top(input g, d, output reg q);
+always_latch if (g) q <= d;
+endmodule
+EOT
+logger -expect-no-warnings
+logger -expect log "Latch inferred for signal .* from always_latch process" 1
+proc -latches error
+logger -check-expected
+select -assert-count 1 t:$dlatch a:always_latch %i
+
+design -reset
+
 # error
 read_verilog <<EOT
 module top(input g, rn, d, output reg q);

tests/various/check_nolatches.ys

@@ -21,6 +21,18 @@ hierarchy -top top
 proc
 check -nolatches -assert
 
+design -reset
+read_verilog -sv <<EOT
+module top(input g, d, output reg q);
+always_latch if (g) q <= d;
+endmodule
+EOT
+hierarchy -top top
+proc
+select -assert-count 1 t:$dlatch a:always_latch %i
+check -nolatches -assert
+check -latchonly -assert
+
 design -reset
 read_verilog <<EOT
 module top(input g, d, output reg q, output y);

tests/various/synth_latch_warning.ys

@@ -14,7 +14,18 @@ design -load read
 synth_ice40 -latches info
 select -assert-count 1 t:SB_LUT4
 
-design -load read
-logger -expect warning "Latch inferred for signal" 1
-logger -expect error "Found 1 problems in 'check -assert'" 1
+# always_latch
+design -reset
+read_verilog -sv <<EOT
+module top(input d, en, output reg q);
+always_latch if (en) q = d;
+endmodule
+EOT
+logger -expect-no-warnings
+synth_ice40
+logger -check-expected
+select -assert-count 1 t:SB_LUT4
+
+design -load read
+logger -expect error "Latch inferred for signal" 1
 synth_ice40