mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-15 03:35:40 +00:00
47 lines
915 B
Text
47 lines
915 B
Text
design -reset
|
|
read_verilog <<EOT
|
|
module top(input g, d, output reg q);
|
|
always @* if (g) q = d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -top top
|
|
proc
|
|
select -assert-count 1 t:$dlatch
|
|
logger -expect warning "is a latch of type" 1
|
|
check -nolatches
|
|
logger -check-expected
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input g, d, output reg q);
|
|
always @* q = g ? d : 1'b0;
|
|
endmodule
|
|
EOT
|
|
hierarchy -top top
|
|
proc
|
|
check -nolatches -assert
|
|
|
|
design -reset
|
|
read_verilog -sv <<EOT
|
|
module top(input g, d, output reg q);
|
|
always_latch if (g) q <= d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -top top
|
|
proc
|
|
select -assert-count 1 t:$dlatch a:always_latch %i
|
|
check -nolatches -assert
|
|
check -latchonly -assert
|
|
|
|
design -reset
|
|
read_verilog <<EOT
|
|
module top(input g, d, output reg q, output y);
|
|
always @* if (g) q = d;
|
|
wire u;
|
|
assign y = u;
|
|
endmodule
|
|
EOT
|
|
hierarchy -top top
|
|
proc
|
|
logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
|
|
check -latchonly -assert
|