mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-15 03:35:40 +00:00
31 lines
640 B
Text
31 lines
640 B
Text
read_verilog <<EOT
|
|
module top(input d, en, output reg q);
|
|
always @* if (en) q = d;
|
|
endmodule
|
|
EOT
|
|
design -save read
|
|
|
|
logger -expect warning "Latch inferred for signal" 1
|
|
synth_ice40 -latches warn
|
|
logger -check-expected
|
|
select -assert-count 1 t:SB_LUT4
|
|
|
|
design -load read
|
|
synth_ice40 -latches info
|
|
select -assert-count 1 t:SB_LUT4
|
|
|
|
# always_latch
|
|
design -reset
|
|
read_verilog -sv <<EOT
|
|
module top(input d, en, output reg q);
|
|
always_latch if (en) q = d;
|
|
endmodule
|
|
EOT
|
|
logger -expect-no-warnings
|
|
synth_ice40
|
|
logger -check-expected
|
|
select -assert-count 1 t:SB_LUT4
|
|
|
|
design -load read
|
|
logger -expect error "Latch inferred for signal" 1
|
|
synth_ice40
|