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5
docs/source/using_yosys/verilog.rst
View file

@ -172,7 +172,10 @@ Verilog Attributes and non-standard features
- The frontend sets attributes ``always_comb``, ``always_latch`` and
``always_ff`` on processes derived from SystemVerilog style always blocks
according to the type of the always. These are checked for correctness in
``proc_dlatch``.
``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt
from the ``proc -latches <info|warn|error>`` reporting policy, and the
generated latch cells carry the ``always_latch`` attribute, which also
exempts them from `check` ``-nolatches``/``-latchonly``.
- The cell attribute ``wildcard_port_conns`` represents wildcard port
connections (SystemVerilog ``.*``). These are resolved to concrete connections

10
passes/cmds/check.cc
View file

@ -63,7 +63,8 @@ struct CheckPass : public Pass {
log(" -nolatches\n");
log(" also check for latch cells ($dlatch, $adlatch, $dlatchsr and their\n");
log(" $_DLATCH_*/$_DLATCHSR_* mappings) remaining in the design. Use this\n");
log(" before techmapping in flows that must not emit latches.\n");
log(" before techmapping in flows that must not emit latches. Cells marked\n");
log(" with the 'always_latch' attribute are not reported.\n");
log("\n");
log(" -latchonly\n");
log(" check only for latch cells (as listed under -nolatches), skipping all\n");
@ -142,10 +143,10 @@ struct CheckPass : public Pass {
// latch-only mode only flags latches, skipping the (potentially false-positive mid-flow) undriven/driver/loop checks below
if (latchonly) {
for (auto cell : module->cells())
if (
if ((
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")
) {
) && !cell->get_bool_attribute(ID::always_latch)) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++;
}
@ -300,7 +301,8 @@ struct CheckPass : public Pass {
if (
nolatches && (
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")) &&
!cell->get_bool_attribute(ID::always_latch)
) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++;

8
passes/proc/proc_dlatch.cc
View file

@ -546,11 +546,16 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
else
cell = db.module->addDlatch(NEW_ID, en, rhs, lhs);
cell->set_src_attribute(src);
if (proc->get_bool_attribute(ID::always_latch))
cell->set_bool_attribute(ID::always_latch);
db.generated_dlatches.insert(cell);
if (proc->get_bool_attribute(ID::always_comb))
log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else if (proc->get_bool_attribute(ID::always_latch))
log("Latch inferred for signal `%s.%s' from always_latch process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
else if (policy == POLICY_ERROR)
log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
@ -580,6 +585,9 @@ struct ProcDlatchPass : public Pass {
log(" -latches <info|warn|error>\n");
log(" controls how the inference of a latch is reported. Alternatively, one\n");
log(" can use the 'proc.latches' scratchpad variable. Defaults to 'warn'.\n");
log(" Latches requested explicitly with 'always_latch' processes are exempt\n");
log(" from this policy and always reported at info level. The generated\n");
log(" latch cells carry the 'always_latch' attribute.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override

3
techlibs/efinix/synth_efinix.cc
View file

@ -68,6 +68,7 @@ struct SynthEfinixPass : public ScriptPass
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -160,7 +161,7 @@ struct SynthEfinixPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
run("proc -latches " + latches);
run("check");
run("flatten");
run("tribuf -logic");

3
techlibs/fabulous/synth_fabulous.cc
View file

@ -115,6 +115,7 @@ struct SynthPass : public ScriptPass {
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -289,7 +290,7 @@ struct SynthPass : public ScriptPass {
run("hierarchy -check");
} else
run(stringf("hierarchy -check -top %s", top_module));
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
run("proc -latches " + latches);
}
if (check_label("flatten", "(unless -noflatten)")) {

3
techlibs/ice40/synth_ice40.cc
View file

@ -122,6 +122,7 @@ struct SynthIce40Pass : public ScriptPass
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -316,7 +317,7 @@ struct SynthIce40Pass : public ScriptPass
{
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
run("proc -latches " + latches);
}
if (check_label("flatten", "(unless -noflatten)"))

3
techlibs/lattice/synth_lattice.cc
View file

@ -161,6 +161,7 @@ struct SynthLatticePass : public ScriptPass
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log(" (ignored with -asyncprld, which has a latch primitive)\n");
log("\n");
log("\n");
@ -416,7 +417,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + ((asyncprld || latches == "info") ? std::string("info") : std::string("warn")));
run("proc -latches " + (asyncprld ? std::string("info") : latches));
if (flatten || help_mode) {
run("check");
run("flatten");

3
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -102,6 +102,7 @@ struct SynthNanoXplorePass : public ScriptPass
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -263,7 +264,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
run("proc -latches " + latches);
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");

3
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -77,6 +77,7 @@ struct SynthQuickLogicPass : public ScriptPass {
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log(" (only applies to the pp3 family)\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -226,7 +227,7 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("prepare")) {
run("proc -latches " + ((family == "pp3" && latches != "info") ? std::string("warn") : std::string("info")));
run("proc -latches " + (family == "pp3" ? latches : std::string("info")));
if (flatten) {
run("check");
run("flatten", "(unless -noflatten)");

14
tests/proc/proc_latches.ys
View file

@ -22,6 +22,20 @@ logger -check-expected
design -reset
# always_latch is exempt
read_verilog -sv <<EOT
module top(input g, d, output reg q);
always_latch if (g) q <= d;
endmodule
EOT
logger -expect-no-warnings
logger -expect log "Latch inferred for signal .* from always_latch process" 1
proc -latches error
logger -check-expected
select -assert-count 1 t:$dlatch a:always_latch %i
design -reset
# error
read_verilog <<EOT
module top(input g, rn, d, output reg q);

12
tests/various/check_nolatches.ys
View file

@ -21,6 +21,18 @@ hierarchy -top top
proc
check -nolatches -assert
design -reset
read_verilog -sv <<EOT
module top(input g, d, output reg q);
always_latch if (g) q <= d;
endmodule
EOT
hierarchy -top top
proc
select -assert-count 1 t:$dlatch a:always_latch %i
check -nolatches -assert
check -latchonly -assert
design -reset
read_verilog <<EOT
module top(input g, d, output reg q, output y);

17
tests/various/synth_latch_warning.ys
View file

@ -14,7 +14,18 @@ design -load read
synth_ice40 -latches info
select -assert-count 1 t:SB_LUT4
design -load read
logger -expect warning "Latch inferred for signal" 1
logger -expect error "Found 1 problems in 'check -assert'" 1
# always_latch
design -reset
read_verilog -sv <<EOT
module top(input d, en, output reg q);
always_latch if (en) q = d;
endmodule
EOT
logger -expect-no-warnings
synth_ice40
logger -check-expected
select -assert-count 1 t:SB_LUT4
design -load read
logger -expect error "Latch inferred for signal" 1
synth_ice40