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input fanout

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This commit is contained in:
Alain Dargelas 2025-03-04 10:52:46 -08:00
parent 104d39057e
commit 3e25ff70ee
1 changed files with 28 additions and 0 deletions
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28
passes/silimate/annotate_cell_fanout.cc
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@ -488,6 +488,24 @@ void calculateFanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
for (auto cell : noFanoutInfo) {
cellFanout[cell] = 1;
}
for (Wire *wire : module->wires()) {
if (wire->port_input) {
SigSpec inp = sigmap(wire);
int fanout = sigFanout[inp];
if (fanout == 0) {
int max = 0;
for (int i = 0; i < inp.size(); i++) {
SigSpec bit_sig = inp.extract(i, 1);
int fa = sigFanout[bit_sig];
max = std::max(max, fa);
}
sigFanout[inp] = max;
}
}
}
}
void splitNet(Design *design, std::set<std::string> &netsToSplitS, RTLIL::SigSpec &sigToSplit, bool formalFriendly, bool inputPort = false)
@ -639,6 +657,8 @@ struct AnnotateCellFanout : public ScriptPass {
int fanout = sigFanout[inp];
if (limit > 0 && (fanout > limit)) {
sigsToFix.emplace(inp, fanout);
} else {
wire->set_string_attribute("$FANOUT", std::to_string(fanout));
}
}
}
@ -661,6 +681,14 @@ struct AnnotateCellFanout : public ScriptPass {
// Add attribute with fanout info to every cell
cell->set_string_attribute("$FANOUT", std::to_string(fanout));
}
for (Wire *wire : module->wires()) {
if (wire->port_input) {
SigSpec inp = sigmap(wire);
int fanout = sigFanout[inp];
// Add attribute with fanout info to every input port
wire->set_string_attribute("$FANOUT", std::to_string(fanout));
}
}
}
}