From 3e25ff70eeb1aabab5abdcec68d1d1daa7c95929 Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain@silimate.com>
Date: Tue, 4 Mar 2025 10:52:46 -0800
Subject: [PATCH] input fanout

---
 passes/silimate/annotate_cell_fanout.cc | 28 +++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/passes/silimate/annotate_cell_fanout.cc b/passes/silimate/annotate_cell_fanout.cc
index c93eb2292..549a84b4d 100644
--- a/passes/silimate/annotate_cell_fanout.cc
+++ b/passes/silimate/annotate_cell_fanout.cc
@@ -488,6 +488,24 @@ void calculateFanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
 	for (auto cell : noFanoutInfo) {
 		cellFanout[cell] = 1;
 	}
+
+	for (Wire *wire : module->wires()) {
+		if (wire->port_input) {
+			SigSpec inp = sigmap(wire);
+			int fanout = sigFanout[inp];
+			if (fanout == 0) {
+				int max = 0;
+				for (int i = 0; i < inp.size(); i++) {
+					SigSpec bit_sig = inp.extract(i, 1);
+					int fa = sigFanout[bit_sig];
+					max = std::max(max, fa);
+				}
+				sigFanout[inp] = max;
+			}
+		}
+	}
+
+
 }
 
 void splitNet(Design *design, std::set<std::string> &netsToSplitS, RTLIL::SigSpec &sigToSplit, bool formalFriendly, bool inputPort = false)
@@ -639,6 +657,8 @@ struct AnnotateCellFanout : public ScriptPass {
 						int fanout = sigFanout[inp];
 						if (limit > 0 && (fanout > limit)) {
 							sigsToFix.emplace(inp, fanout);
+						} else {
+							wire->set_string_attribute("$FANOUT", std::to_string(fanout));
 						}
 					}
 				}
@@ -661,6 +681,14 @@ struct AnnotateCellFanout : public ScriptPass {
 					// Add attribute with fanout info to every cell
 					cell->set_string_attribute("$FANOUT", std::to_string(fanout));
 				}
+				for (Wire *wire : module->wires()) {
+					if (wire->port_input) {
+						SigSpec inp = sigmap(wire);
+						int fanout = sigFanout[inp];
+						// Add attribute with fanout info to every input port
+						wire->set_string_attribute("$FANOUT", std::to_string(fanout));
+					}
+				}
 			}
 		}