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https://github.com/YosysHQ/yosys
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unique names
This commit is contained in:
Alain Dargelas
parent
fd2ac3ad8d
commit
104d39057e
1 changed files with 52 additions and 36 deletions
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@ -5,14 +5,24 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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RTLIL::IdString generateSigSpecName(const RTLIL::SigSpec &sigspec)
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// Return substring up to a delimiter or full string if not found
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std::string substringuntil(const std::string &str, char delimiter)
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{
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size_t pos = str.find(delimiter);
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if (pos != std::string::npos) {
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return str.substr(0, pos);
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} else {
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return str;
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}
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}
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// Generate a human readable name for a sigspec, uniquify if necessary
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RTLIL::IdString generateSigSpecName(Module* module, const RTLIL::SigSpec &sigspec, bool makeUnique = false, std::string postfix = "", bool cellName = false)
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{
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if (sigspec.empty()) {
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return RTLIL::IdString(); // Empty SigSpec, return empty IdString
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}
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std::stringstream ss;
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if (sigspec.is_wire()) {
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// Handle wires
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ss << sigspec.as_wire()->name.str();
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@ -22,33 +32,47 @@ RTLIL::IdString generateSigSpecName(const RTLIL::SigSpec &sigspec)
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if (sigspec[0].wire->width != 1) {
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ss << "[" << sigspec[0].offset << "]";
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}
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} else if (sigspec.is_chunk()) {
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// Handle slices
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RTLIL::Wire *parent_wire = sigspec[0].wire;
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SigChunk chunk = sigspec.as_chunk();
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if (parent_wire) {
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ss << parent_wire->name.str() << "[" << chunk.offset + chunk.width - 1 << ":" << chunk.offset << "]";
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}
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} else if (!sigspec.is_chunk()) {
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// Handle vector of chunks
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int max = 0;
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int min = INT_MAX;
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RTLIL::Wire *parent_wire = sigspec[0].wire;
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int width = 0;
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for (SigChunk chunk : sigspec.chunks()) {
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width += chunk.width;
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max = std::max(max, chunk.offset);
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min = std::min(min, chunk.offset);
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}
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if (max == 0) {
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max = width - 1;
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}
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if (parent_wire) {
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ss << parent_wire->name.str() << "[" << max << ":" << min << "]";
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if (max != min) {
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ss << substringuntil(parent_wire->name.str(), '[') << "[" << max << ":" << min << "]";
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} else {
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ss << parent_wire->name.str();
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}
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} else {
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ss << "\\sigspec_[" << max << ":" << min << "]";
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}
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} else {
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// Handle other cases (e.g., constants)
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ss << "\\sigspec_";
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}
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ss << postfix;
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if (makeUnique) {
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RTLIL::IdString base_name = RTLIL::IdString(ss.str());
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// Ensure uniqueness
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int counter = 0;
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if (cellName) {
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while (module->cells_.count(RTLIL::IdString(ss.str()))) {
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ss.str("");
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ss << base_name.str() << "_" << counter++;
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}
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} else {
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while (module->wires_.count(RTLIL::IdString(ss.str()))) {
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ss.str("");
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ss << base_name.str() << "_" << counter++;
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}
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}
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}
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RTLIL::IdString base_name = RTLIL::IdString(ss.str());
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return RTLIL::IdString(ss.str());
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}
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@ -111,6 +135,7 @@ void lhs2rhs_rhs2lhs(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
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}
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}
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// Returns the parent wire of a sigspec
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RTLIL::Wire *getParentWire(const RTLIL::SigSpec &sigspec)
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{
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if (sigspec.empty()) {
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@ -216,7 +241,7 @@ RTLIL::SigSpec getCellOutputSigSpec(Cell *cell, SigMap &sigmap)
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}
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// Get new output signal for a given signal, used all datastructures with change to buffer
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SigSpec updateToBuffer(std::map<SigSpec, int> &bufferIndexes,
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SigSpec updateToBuffer(Module* module, std::map<SigSpec, int> &bufferIndexes,
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std::map<RTLIL::SigSpec, std::vector<std::pair<RTLIL::SigSpec, Cell *>>> &buffer_outputs,
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dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout, std::map<Cell *, int> &bufferActualFanout,
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std::map<SigSpec, SigSpec> &usedBuffers, int max_output_per_buffer, Cell *fanoutcell, SigSpec sigToReplace,
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@ -229,7 +254,7 @@ SigSpec updateToBuffer(std::map<SigSpec, int> &bufferIndexes,
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std::map<SigSpec, SigSpec>::iterator itrBuffer = usedBuffers.find(sigToReplace);
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if (itrBuffer != usedBuffers.end()) {
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if (debug)
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std::cout << "REUSE CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(sigToReplace).c_str()
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std::cout << "REUSE CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(module, sigToReplace).c_str()
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<< std::endl;
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return itrBuffer->second;
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}
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@ -259,8 +284,8 @@ SigSpec updateToBuffer(std::map<SigSpec, int> &bufferIndexes,
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}
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// Cache result
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if (debug)
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std::cout << "CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(sigToReplace).c_str() << " BY "
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<< generateSigSpecName(newSig).c_str() << std::endl;
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std::cout << "CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(module, sigToReplace).c_str() << " BY "
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<< generateSigSpecName(module, newSig).c_str() << std::endl;
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usedBuffers.emplace(sigToReplace, newSig);
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// Return buffer's output
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@ -279,7 +304,7 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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if (sigToBuffer.is_fully_const()) {
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return;
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}
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std::string signame = generateSigSpecName(sigToBuffer).c_str();
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std::string signame = generateSigSpecName(module, sigToBuffer).c_str();
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if (fanout <= limit) {
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if (debug) {
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std::cout << "Nothing to do for: " << signame << std::endl;
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@ -318,9 +343,11 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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for (SigChunk chunk : sigToBuffer.chunks()) {
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std::vector<std::pair<RTLIL::SigSpec, Cell *>> buffer_chunk_outputs;
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for (int i = 0; i < num_buffers; ++i) {
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RTLIL::Cell *buffer = module->addCell(signame + "_fbuf" + std::to_string(index_buffer), ID($pos));
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std::string wireName = generateSigSpecName(module, sigToBuffer, true, "_wbuf" + std::to_string(index_buffer)).c_str();
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std::string cellName = generateSigSpecName(module, sigToBuffer, true, "_fbuf" + std::to_string(index_buffer), true).c_str();
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RTLIL::Cell *buffer = module->addCell(cellName, ID($pos));
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bufferActualFanout[buffer] = 0;
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RTLIL::SigSpec buffer_output = module->addWire(signame + "_wbuf" + std::to_string(index_buffer), chunk.size());
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RTLIL::SigSpec buffer_output = module->addWire(wireName, chunk.size());
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buffer->setPort(ID(A), chunk);
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buffer->setPort(ID(Y), sigmap(buffer_output));
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buffer->fixup_parameters();
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@ -359,7 +386,7 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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if (debug)
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std::cout << " MATCH" << std::endl;
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// Input is one of the cell's outputs, its a match
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SigSpec newSig = updateToBuffer(bufferIndexes, buffer_outputs, sig2CellsInFanout, bufferActualFanout,
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SigSpec newSig = updateToBuffer(module, bufferIndexes, buffer_outputs, sig2CellsInFanout, bufferActualFanout,
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usedBuffers, max_output_per_buffer, fanoutcell, actual, debug);
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// Override the fanout cell's input with the buffer output
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fanoutcell->setPort(portName, newSig);
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@ -376,7 +403,7 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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if (debug)
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std::cout << " MATCH" << std::endl;
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SigSpec newSig =
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updateToBuffer(bufferIndexes, buffer_outputs, sig2CellsInFanout, bufferActualFanout,
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updateToBuffer(module, bufferIndexes, buffer_outputs, sig2CellsInFanout, bufferActualFanout,
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usedBuffers, max_output_per_buffer, fanoutcell, chunk, debug);
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// Append the buffer's output in the chunk vector
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newChunks.push_back(newSig.as_chunk());
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@ -463,17 +490,6 @@ void calculateFanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
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}
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}
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// Return substring up to a delimiter or full string if not found
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std::string substringuntil(const std::string &str, char delimiter)
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{
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size_t pos = str.find(delimiter);
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if (pos != std::string::npos) {
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return str.substr(0, pos);
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} else {
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return str;
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}
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}
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void splitNet(Design *design, std::set<std::string> &netsToSplitS, RTLIL::SigSpec &sigToSplit, bool formalFriendly, bool inputPort = false)
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{
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Wire *parentWire = getParentWire(sigToSplit);
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