From 725c489c7e1daa928030d8be6842892db1c0f175 Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Sat, 15 Mar 2025 17:11:32 +0200
Subject: [PATCH 1/4] ice40_dsp: fix log_assert issue
---
techlibs/ice40/ice40_dsp.pmg | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg
index 9099dd3c4..285e3ceee 100644
--- a/techlibs/ice40/ice40_dsp.pmg
+++ b/techlibs/ice40/ice40_dsp.pmg
@@ -46,17 +46,19 @@ code sigA sigB sigH
// Only care about those bits that are used
int i;
- for (i = 0; i < GetSize(O); i++) {
- if (nusers(O[i]) <= 1)
- break;
- sigH.append(O[i]);
- }
+ for (i = GetSize(O) - 1; i > 0 && nusers(O[i]) <= 1; i--)
+ ;
// This sigM could have no users if downstream sinks (e.g. $add) is
// narrower than $mul result, for example
if (i == 0)
reject;
- log_assert(nusers(O.extract_end(i)) <= 1);
+ for (int j = 0; j <= i; j++)
+ if (nusers(O[j]) == 0)
+ sigH.append(module->addWire(NEW_ID));
+ else
+ sigH.append(O[j]);
+
endcode
code argQ ffA sigA clock clock_pol
From 5ae32efca5a2018ce8ef41fa1cb30590b0a8aed5 Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Sat, 15 Mar 2025 20:05:57 +0200
Subject: [PATCH 2/4] ice40_dsp: add test
---
tests/various/bug4865.ys | 67 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 tests/various/bug4865.ys
diff --git a/tests/various/bug4865.ys b/tests/various/bug4865.ys
new file mode 100644
index 000000000..ac5a459d8
--- /dev/null
+++ b/tests/various/bug4865.ys
@@ -0,0 +1,67 @@
+read_rtlil << EOF
+
+autoidx 524
+
+attribute \top 1
+attribute \library "work"
+attribute \hdlname "main"
+module \main
+
+ attribute \force_downto 1
+ wire width 18 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0]
+
+ wire width 14 $delete_wire$514
+
+ attribute \module_not_derived 1
+ cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
+ parameter \A_REG 1'0
+ parameter \A_SIGNED 0
+ parameter \BOTADDSUB_CARRYSELECT 2'00
+ parameter \BOTADDSUB_LOWERINPUT 2'00
+ parameter \BOTADDSUB_UPPERINPUT 1'0
+ parameter \BOTOUTPUT_SELECT 2'11
+ parameter \BOT_8x8_MULT_REG 1'0
+ parameter \B_REG 1'0
+ parameter signed \B_SIGNED 0
+ parameter \C_REG 1'0
+ parameter \D_REG 1'0
+ parameter \MODE_8x8 1'0
+ parameter \NEG_TRIGGER 1'0
+ parameter \PIPELINE_16x16_MULT_REG1 1'0
+ parameter \PIPELINE_16x16_MULT_REG2 1'0
+ parameter \TOPADDSUB_CARRYSELECT 2'00
+ parameter \TOPADDSUB_LOWERINPUT 2'00
+ parameter \TOPADDSUB_UPPERINPUT 1'0
+ parameter \TOPOUTPUT_SELECT 2'11
+ parameter \TOP_8x8_MULT_REG 1'0
+ connect \A 16'x
+ connect \B 16'x
+ connect \O { $delete_wire$514 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:2] 2'x}
+ end
+
+ cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.etc.sliceA.last.$add$/home/emil/pulls/yosys/share/mul2dsp.v:216$483
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 18
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 19
+ connect \A 18'x
+ connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:16]
+ connect \Y 19'x
+ end
+
+ cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.$add$/home/emil/pulls/yosys/share/mul2dsp.v:173$480
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 14
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 2
+ connect \A $delete_wire$514
+ connect \B 2'x
+ connect \Y 2'x
+ end
+
+end
+EOF
+
+ice40_dsp
From a9d765e11ef04fda65de4027f1d4b5fa87370f0f Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Sun, 16 Mar 2025 15:11:45 +0200
Subject: [PATCH 3/4] ice40_dsp: group empty wires
---
techlibs/ice40/ice40_dsp.pmg | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg
index 285e3ceee..63bc8de4b 100644
--- a/techlibs/ice40/ice40_dsp.pmg
+++ b/techlibs/ice40/ice40_dsp.pmg
@@ -53,11 +53,16 @@ code sigA sigB sigH
if (i == 0)
reject;
- for (int j = 0; j <= i; j++)
+ for (int j = 0, wire_width = 0; j <= i; j++)
if (nusers(O[j]) == 0)
- sigH.append(module->addWire(NEW_ID));
- else
+ wire_width++;
+ else {
+ if (wire_width) { // add empty wires for bit offset if needed
+ sigH.append(module->addWire(NEW_ID, wire_width));
+ wire_width = 0;
+ }
sigH.append(O[j]);
+ }
endcode
From cb03a1ec2121cde499253c8f3738bac8fdb400b0 Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Wed, 26 Mar 2025 15:13:05 +0200
Subject: [PATCH 4/4] ice40_dsp: fix test
---
tests/various/bug4865.ys | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/tests/various/bug4865.ys b/tests/various/bug4865.ys
index ac5a459d8..b747c59a7 100644
--- a/tests/various/bug4865.ys
+++ b/tests/various/bug4865.ys
@@ -1,5 +1,6 @@
read_rtlil << EOF
+
autoidx 524
attribute \top 1
@@ -10,8 +11,10 @@ module \main
attribute \force_downto 1
wire width 18 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0]
- wire width 14 $delete_wire$514
+ wire width 12 $delete_wire$514
+ wire width 4 $test
+
attribute \module_not_derived 1
cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
parameter \A_REG 1'0
@@ -36,7 +39,7 @@ module \main
parameter \TOP_8x8_MULT_REG 1'0
connect \A 16'x
connect \B 16'x
- connect \O { $delete_wire$514 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:2] 2'x}
+ connect \O { $test $delete_wire$514 14'x $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0] }
end
cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.etc.sliceA.last.$add$/home/emil/pulls/yosys/share/mul2dsp.v:216$483
@@ -46,17 +49,17 @@ module \main
parameter \B_WIDTH 2
parameter \Y_WIDTH 19
connect \A 18'x
- connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:16]
+ connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0]
connect \Y 19'x
end
cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.$add$/home/emil/pulls/yosys/share/mul2dsp.v:173$480
parameter \A_SIGNED 0
- parameter \A_WIDTH 14
+ parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $delete_wire$514
+ connect \A $delete_wire$514 [1:0]
connect \B 2'x
connect \Y 2'x
end