From 176faae7c94b0dea13052b17d4f210cb19b2d7ba Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 10 Mar 2025 11:43:13 +0100
Subject: [PATCH] opt_merge: fix trivial binary regression

---
 passes/opt/opt_merge.cc      |  1 -
 tests/opt/opt_merge_basic.ys | 13 +++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 tests/opt/opt_merge_basic.ys

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 1992aa871..745b27e87 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -95,7 +95,6 @@ struct OptMergeWorker
 			};
 			std::sort(inputs.begin(), inputs.end());
 			h = hash_ops<std::array<RTLIL::SigSpec, 2>>::hash_into(inputs, h);
-			h = assign_map(cell->getPort(ID::Y)).hash_into(h);
 		} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
 			SigSpec a = assign_map(cell->getPort(ID::A));
 			a.sort();
diff --git a/tests/opt/opt_merge_basic.ys b/tests/opt/opt_merge_basic.ys
new file mode 100644
index 000000000..e6336f648
--- /dev/null
+++ b/tests/opt/opt_merge_basic.ys
@@ -0,0 +1,13 @@
+read_verilog -icells <<EOT
+module top(A, B, X, Y);
+input [8:0] A, B;
+output [8:0] X, Y;
+assign X = A + B;
+assign Y = A + B;
+endmodule
+EOT
+
+select -assert-count 2 t:$add
+equiv_opt -assert opt_merge
+design -load postopt
+select -assert-count 1 t:$add