mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 01:54:10 +00:00
14 lines
248 B
Plaintext
14 lines
248 B
Plaintext
read_verilog -icells <<EOT
|
|
module top(A, B, X, Y);
|
|
input [8:0] A, B;
|
|
output [8:0] X, Y;
|
|
assign X = A + B;
|
|
assign Y = A + B;
|
|
endmodule
|
|
EOT
|
|
|
|
select -assert-count 2 t:$add
|
|
equiv_opt -assert opt_merge
|
|
design -load postopt
|
|
select -assert-count 1 t:$add
|