Merge b3b1394cf1 into c9805ceb33

tests/arch/ecp5/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
+synth_ecp5 -latches info
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT4
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
+synth_ecp5 -latches info
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT4
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
+synth_ecp5 -latches info
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT4
 select -assert-count 1 t:PFUMX

tests/arch/ecp5/latches_abc9.ys

@@ -8,6 +8,6 @@ assign q = ~l;
 endmodule
 EOT
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5 -abc9
+synth_ecp5 -abc9 -latches info
 select -assert-count 2 t:LUT4
 select -assert-none t:LUT4 %% t:* %D

tests/arch/efinix/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_efinix -latches info
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_LUT4
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_efinix -latches info
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_LUT4
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_efinix -latches info
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:EFX_LUT4
 

tests/arch/ice40/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ice40
+synth_ice40 -latches info
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_LUT4
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ice40
+synth_ice40 -latches info
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_LUT4
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ice40
+synth_ice40 -latches info
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:SB_LUT4
 

tests/arch/nanoxplore/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore -noiopad
+synth_nanoxplore -noiopad -latches info
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore -noiopad
+synth_nanoxplore -noiopad -latches info
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore -noiopad
+synth_nanoxplore -noiopad -latches info
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:NX_LUT
 

tests/arch/quicklogic/pp3/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic
+synth_quicklogic -latches info
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
 select -assert-count 3 t:inpad
@@ -17,7 +17,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic
+synth_quicklogic -latches info
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
 select -assert-count 3 t:inpad
@@ -30,7 +30,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic
+synth_quicklogic -latches info
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT2
 select -assert-count 1 t:LUT4

tests/proc/proc_latches.ys

@@ -0,0 +1,32 @@
+# warn
+read_verilog <<EOT
+module top(input g, rn, d, output reg q);
+always @* if (~rn) q <= 0; else if (g) q <= d;
+endmodule
+EOT
+logger -expect warning "Latch inferred for signal" 1
+proc
+logger -check-expected
+
+design -reset
+
+# info
+read_verilog <<EOT
+module top(input g, rn, d, output reg q);
+always @* if (~rn) q <= 0; else if (g) q <= d;
+endmodule
+EOT
+logger -expect-no-warnings
+proc -latches info
+logger -check-expected
+
+design -reset
+
+# error
+read_verilog <<EOT
+module top(input g, rn, d, output reg q);
+always @* if (~rn) q <= 0; else if (g) q <= d;
+endmodule
+EOT
+logger -expect error "Latch inferred for signal" 1
+proc -latches error

tests/various/check_nolatches.ys

@@ -0,0 +1,47 @@
+read_verilog <<EOT
+module top(input g, rn, d, output reg q);
+always @* if (~rn) q <= 0; else if (g) q <= d;
+endmodule
+EOT
+proc
+select -assert-count 1 t:$dlatch
+logger -expect warning "is a latch of type" 1
+check -nolatches
+logger -check-expected
+
+design -reset
+
+read_verilog <<EOT
+module top(input g, d, output reg q);
+always @* q = g ? d : 1'b0;
+endmodule
+EOT
+proc
+check -nolatches -assert
+
+design -reset
+
+read_verilog <<EOT
+module top(input g, rn, d, output reg q);
+always @* if (~rn) q <= 0; else if (g) q <= d;
+endmodule
+EOT
+proc
+logger -expect error "Found 1 problems in" 1
+check -nolatches -assert
+
+design -reset
+
+read_verilog <<EOT
+module top(input g, d, output reg q, output y);
+always @* if (g) q = d;
+wire u;
+assign y = u;
+endmodule
+EOT
+proc
+scratchpad -set check.latchonly 1
+logger -expect warning "is a latch of type" 1
+logger -expect warning "used but has no driver" 0
+logger -expect error "Found 1 problems in" 1
+check -assert

tests/various/synth_latch_warning.ys

@@ -0,0 +1,20 @@
+read_verilog <<EOT
+module top(input d, en, output reg q);
+always @* if (en) q = d;
+endmodule
+EOT
+design -save read
+
+logger -expect warning "Latch inferred for signal" 1
+synth_ice40 -latches warn
+logger -check-expected
+select -assert-count 1 t:SB_LUT4
+
+design -load read
+synth_ice40 -latches info
+select -assert-count 1 t:SB_LUT4
+
+design -load read
+logger -expect warning "Latch inferred for signal" 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+synth_ice40