diff --git a/docs/source/code_examples/macro_commands/synth_ice40.ys b/docs/source/code_examples/macro_commands/synth_ice40.ys index 07d960a64..a829c197c 100644 --- a/docs/source/code_examples/macro_commands/synth_ice40.ys +++ b/docs/source/code_examples/macro_commands/synth_ice40.ys @@ -67,6 +67,7 @@ map_ffs: map_luts: abc ice40_opt + check techmap simplemap techmap diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 426216800..de077415f 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -60,6 +60,11 @@ struct CheckPass : public Pass { log(" also check for internal cells that have not been mapped to cells of the\n"); log(" target architecture\n"); log("\n"); + log(" -nolatches\n"); + log(" also check for latch cells ($dlatch, $adlatch, $dlatchsr and their\n"); + log(" $_DLATCH_*/$_DLATCHSR_* mappings) remaining in the design. Use this\n"); + log(" before techmapping in flows that must not emit latches.\n"); + log("\n"); log(" -allow-tbuf\n"); log(" modify the -mapped behavior to still allow $_TBUF_ cells\n"); log("\n"); @@ -79,6 +84,7 @@ struct CheckPass : public Pass { bool noinit = false; bool initdrv = false; bool mapped = false; + bool nolatches = false; bool allow_tbuf = false; bool assert_mode = false; bool force_detailed_loop_check = false; @@ -98,6 +104,10 @@ struct CheckPass : public Pass { mapped = true; continue; } + if (args[argidx] == "-nolatches") { + nolatches = true; + continue; + } if (args[argidx] == "-allow-tbuf") { allow_tbuf = true; continue; @@ -114,12 +124,27 @@ struct CheckPass : public Pass { } extra_args(args, argidx, design); + bool latchonly = design->scratchpad_get_bool("check.latchonly", false); + log_header(design, "Executing CHECK pass (checking for obvious problems).\n"); for (auto module : design->selected_whole_modules_warn()) { log("Checking module %s...\n", module); + // latch-only mode only flags latches, skipping the (potentially false-positive mid-flow) undriven/driver/loop checks below + if (latchonly) { + for (auto cell : module->cells()) + if ( + cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) || + cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_") + ) { + log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape()); + counter++; + } + continue; + } + SigMap sigmap(module); dict> wire_drivers; dict driver_cells; @@ -265,6 +290,15 @@ struct CheckPass : public Pass { cell_allowed:; } + if ( + nolatches && ( + cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) || + cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")) + ) { + log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape()); + counter++; + } + for (auto &conn : cell->connections()) { bool input = cell->input(conn.first); bool output = cell->output(conn.first); diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index c18651d5e..d781d9047 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -69,10 +69,14 @@ struct ProcPass : public Pass { log(" -noopt\n"); log(" Will omit the opt_expr pass.\n"); log("\n"); + log(" -latches \n"); + log(" controls how the inference of a latch is reported.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { std::string global_arst; + std::string latches; bool ifxmode = false; bool nomux = false; bool noopt = false; @@ -104,6 +108,10 @@ struct ProcPass : public Pass { norom = true; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -121,7 +129,10 @@ struct ProcPass : public Pass { Pass::call(design, "proc_rom"); if (!nomux) Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux"); - Pass::call(design, "proc_dlatch"); + if (latches.empty()) + Pass::call(design, "proc_dlatch"); + else + Pass::call(design, "proc_dlatch -latches " + latches); Pass::call(design, "proc_dff"); Pass::call(design, "proc_memwr"); Pass::call(design, "proc_clean"); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 50e64f482..5e710d60b 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -345,7 +345,13 @@ struct proc_dlatch_db_t } }; -void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) +enum LatchPolicy { + POLICY_INFO, + POLICY_WARN, + POLICY_ERROR +}; + +void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy) { RTLIL::SigSig latches_bits, nolatches_bits; dict latches_out_in; @@ -443,6 +449,12 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) if (proc->get_bool_attribute(ID::always_comb)) log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + else if (policy == POLICY_ERROR) + log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", + db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); + else if (policy == POLICY_WARN) + log_warning("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", + db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); else log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); @@ -458,22 +470,49 @@ struct ProcDlatchPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" proc_dlatch [selection]\n"); + log(" proc_dlatch [options] [selection]\n"); log("\n"); log("This pass identifies latches in the processes and converts them to\n"); log("d-type latches.\n"); log("\n"); + log(" -latches \n"); + log(" controls how the inference of a latch is reported. Alternatively, one\n"); + log(" can use the 'proc.latches' scratchpad variable. Defaults to 'warn'.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n"); - extra_args(args, 1, design); + std::string policy_str; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + policy_str = args[++argidx]; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (policy_str.empty()) + policy_str = design->scratchpad_get_string("proc.latches", "warn"); + + LatchPolicy policy; + if (policy_str == "info") + policy = POLICY_INFO; + else if (policy_str == "warn") + policy = POLICY_WARN; + else if (policy_str == "error") + policy = POLICY_ERROR; + else + log_cmd_error("Invalid value '%s' for -latches (expected info|warn|error).\n", policy_str.c_str()); for (auto mod : design->all_selected_modules()) { proc_dlatch_db_t db(mod); for (auto proc : mod->selected_processes()) - proc_dlatch(db, proc); + proc_dlatch(db, proc, policy); db.fixup_muxes(); } } diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 00d884107..3656218c5 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -78,6 +78,9 @@ struct SynthPass : public ScriptPass { log(" -nordff\n"); log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n"); log("\n"); + log(" -latches \n"); + log(" controls how the inference of a latch is reported.\n"); + log("\n"); log(" -noshare\n"); log(" do not run SAT-based resource sharing\n"); log("\n"); @@ -111,7 +114,7 @@ struct SynthPass : public ScriptPass { log("\n"); } - string top_module, fsm_opts, memory_opts, abc; + string top_module, fsm_opts, memory_opts, abc, latches_opt; bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, arith_tree, hieropt, relative_share; int lut; std::vector techmap_maps; @@ -121,6 +124,7 @@ struct SynthPass : public ScriptPass { top_module.clear(); fsm_opts.clear(); memory_opts.clear(); + latches_opt.clear(); autotop = false; flatten = false; @@ -200,6 +204,10 @@ struct SynthPass : public ScriptPass { memory_opts += " -nordff"; continue; } + if (args[argidx] == "-latches" && argidx + 1 < args.size()) { + latches_opt += " -latches " + args[++argidx]; + continue; + } if (args[argidx] == "-noshare") { noshare = true; continue; @@ -276,7 +284,7 @@ struct SynthPass : public ScriptPass { } if (check_label("coarse")) { - run("proc"); + run("proc" + latches_opt); if (flatten || help_mode) { run("check"); run("flatten", " (if -flatten)"); diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 14457c64b..60d72895c 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -63,13 +63,19 @@ struct SynthEfinixPass : public ScriptPass log(" -nobram\n"); log(" do not use EFX_RAM_5K cells in output netlist\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, edif_file, json_file; + string top_opt, edif_file, json_file, latches; bool flatten, retime, nobram; void clear_flags() override @@ -80,6 +86,7 @@ struct SynthEfinixPass : public ScriptPass flatten = true; retime = false; nobram = false; + latches = "error"; } void execute(std::vector args, RTLIL::Design *design) override @@ -122,12 +129,18 @@ struct SynthEfinixPass : public ScriptPass nobram = true; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); log_header(design, "Executing SYNTH_EFINIX pass.\n"); log_push(); @@ -147,7 +160,7 @@ struct SynthEfinixPass : public ScriptPass if (flatten && check_label("flatten", "(unless -noflatten)")) { - run("proc"); + run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); run("check"); run("flatten"); run("tribuf -logic"); @@ -190,6 +203,13 @@ struct SynthEfinixPass : public ScriptPass if (check_label("map_ffs")) { run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x"); + if (help_mode) + run("check -assert", "(only if -latches error, the default)"); + else if (latches == "error") { + active_design->scratchpad_set_bool("check.latchonly", true); + run("check -assert"); + active_design->scratchpad_unset("check.latchonly"); + } run("techmap -D NO_LUT -map +/efinix/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0074a52af..57d4286f4 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -116,13 +116,19 @@ struct SynthPass : public ScriptPass log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" attribute on all memories).\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode; + string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode, latches; std::vector extra_plib, extra_map; bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; @@ -144,6 +150,7 @@ struct SynthPass : public ScriptPass flatten = true; json_file = ""; blif_file = ""; + latches = "error"; } void execute(std::vector args, RTLIL::Design *design) override @@ -243,12 +250,18 @@ struct SynthPass : public ScriptPass flatten = false; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); log_header(design, "Executing SYNTH_FABULOUS pass.\n"); log_push(); @@ -279,7 +292,7 @@ struct SynthPass : public ScriptPass run("hierarchy -check"); } else run(stringf("hierarchy -check -top %s", top_module)); - run("proc"); + run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); } @@ -359,6 +372,13 @@ struct SynthPass : public ScriptPass } else { run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff"); } + if (help_mode) + run("check -assert", "(only if -latches error, the default)"); + else if (latches == "error") { + active_design->scratchpad_set_bool("check.latchonly", true); + run("check -assert"); + active_design->scratchpad_unset("check.latchonly"); + } run("techmap -map +/fabulous/latches_map.v"); run("techmap -map +/fabulous/ff_map.v"); if (help_mode) { diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 86189c848..5a27d5de8 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -117,13 +117,19 @@ struct SynthIce40Pass : public ScriptPass log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" attribute on all memories).\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, blif_file, edif_file, json_file, device_opt; + string top_opt, blif_file, edif_file, json_file, device_opt, latches; bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap, no_rw_check; int min_ce_use; @@ -148,6 +154,7 @@ struct SynthIce40Pass : public ScriptPass flowmap = false; device_opt = "hx"; no_rw_check = false; + latches = "error"; } void execute(std::vector args, RTLIL::Design *design) override @@ -258,6 +265,10 @@ struct SynthIce40Pass : public ScriptPass no_rw_check = true; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -266,6 +277,8 @@ struct SynthIce40Pass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") log_cmd_error("Invalid or no device specified: '%s'\n", device_opt); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); if (abc9 && retime) log_cmd_error("-retime option not currently compatible with -abc9!\n"); @@ -303,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass { run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); - run("proc"); + run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); } if (check_label("flatten", "(unless -noflatten)")) @@ -406,6 +419,13 @@ struct SynthIce40Pass : public ScriptPass run("abc", " (only if -abc2)"); run("ice40_opt", "(only if -abc2)"); } + if (help_mode) + run("check -assert", "(only if -latches error, the default)"); + else if (latches == "error") { + active_design->scratchpad_set_bool("check.latchonly", true); + run("check -assert"); + active_design->scratchpad_unset("check.latchonly"); + } run("techmap -map +/ice40/latches_map.v"); if (noabc || flowmap || help_mode) { run("simplemap", " (if -noabc or -flowmap)"); diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index 43fb7b1c2..ec3520616 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -156,13 +156,20 @@ struct SynthLatticePass : public ScriptPass log(" implement constant comparisons in soft logic, do not involve\n"); log(" hard carry chains\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" (ignored with -asyncprld, which has a latch primitive)\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, edif_file, json_file, family; + string top_opt, edif_file, json_file, family, latches; bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; bool cmp2softlogic; string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc; @@ -189,6 +196,7 @@ struct SynthLatticePass : public ScriptPass iopad = false; nodsp = false; no_rw_check = false; + latches = "error"; postfix = ""; arith_map = ""; brams_map = ""; @@ -318,6 +326,10 @@ struct SynthLatticePass : public ScriptPass cmp2softlogic = true; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -325,6 +337,9 @@ struct SynthLatticePass : public ScriptPass if (family.empty()) log_cmd_error("Lattice family parameter must be set.\n"); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); + if (family == "ecp5") { postfix = "_ecp5"; arith_map = "_ccu2c"; @@ -401,7 +416,7 @@ struct SynthLatticePass : public ScriptPass if (check_label("coarse")) { - run("proc"); + run("proc -latches " + ((asyncprld || latches == "info") ? std::string("info") : std::string("warn"))); if (flatten || help_mode) { run("check"); run("flatten"); @@ -531,8 +546,16 @@ struct SynthLatticePass : public ScriptPass { if (abc2 || help_mode) run("abc", " (only if -abc2)"); - if (!asyncprld || help_mode) + if (!asyncprld || help_mode) { + if (help_mode) + run("check -assert", "(skip if -asyncprld; only if -latches error, the default)"); + else if (latches == "error") { + active_design->scratchpad_set_bool("check.latchonly", true); + run("check -assert"); + active_design->scratchpad_unset("check.latchonly"); + } run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); + } if (abc9) { std::string abc9_opts; diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 0b87c98c7..9aeb6e2d4 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -97,13 +97,19 @@ struct SynthNanoXplorePass : public ScriptPass log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" attribute on all memories).\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, json_file, family; + string top_opt, json_file, family, latches; bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check; std::string postfix; int min_ce_use, min_srst_use; @@ -124,6 +130,7 @@ struct SynthNanoXplorePass : public ScriptPass postfix = ""; min_ce_use = 8; min_srst_use = 8; + latches = "error"; } void execute(std::vector args, RTLIL::Design *design) override @@ -202,10 +209,17 @@ struct SynthNanoXplorePass : public ScriptPass no_rw_check = true; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); + if (family.empty()) { //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); family = "ultra"; @@ -249,7 +263,7 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("coarse")) { - run("proc"); + run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); if (flatten || help_mode) { run("check"); run("flatten", "(skip if -noflatten)"); @@ -325,6 +339,13 @@ struct SynthNanoXplorePass : public ScriptPass dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use); run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("opt_merge"); + if (help_mode) + run("check -assert", "(only if -latches error, the default)"); + else if (latches == "error") { + active_design->scratchpad_set_bool("check.latchonly", true); + run("check -assert"); + active_design->scratchpad_unset("check.latchonly"); + } run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/cells_map.v"); run("opt_expr -undriven -mux_undef"); diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index e65be1c58..4458fdea5 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -72,12 +72,19 @@ struct SynthQuickLogicPass : public ScriptPass { log(" use old ABC flow, which has generally worse mapping results but is less\n"); log(" likely to have bugs.\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" (only applies to the pp3 family)\n"); + log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; + string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path, latches; bool abc9, inferAdder, nobram, bramTypes, dsp, ioff, flatten; void clear_flags() override @@ -96,6 +103,7 @@ struct SynthQuickLogicPass : public ScriptPass { dsp = true; ioff = true; flatten = true; + latches = "error"; } void set_scratchpad_defaults(RTLIL::Design *design) { @@ -168,6 +176,10 @@ struct SynthQuickLogicPass : public ScriptPass { flatten = false; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -178,6 +190,9 @@ struct SynthQuickLogicPass : public ScriptPass { if (family != "pp3" && family != "qlf_k6n10f") log_cmd_error("Invalid family specified: '%s'\n", family); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); + if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n"); design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay. @@ -211,7 +226,7 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("prepare")) { - run("proc"); + run("proc -latches " + ((family == "pp3" && latches != "info") ? std::string("warn") : std::string("info"))); if (flatten) { run("check"); run("flatten", "(unless -noflatten)"); @@ -315,6 +330,13 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { + if (help_mode) + run("check -assert", "(only if -latches error, the default)"); + else if (latches == "error") { + active_design->scratchpad_set_bool("check.latchonly", true); + run("check -assert"); + active_design->scratchpad_unset("check.latchonly"); + } run("techmap -map " + lib_path + family + "/latches_map.v"); if (abc9) { run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v"); diff --git a/tests/arch/ecp5/latches.ys b/tests/arch/ecp5/latches.ys index 3d011d74f..0785b6fc2 100644 --- a/tests/arch/ecp5/latches.ys +++ b/tests/arch/ecp5/latches.ys @@ -4,7 +4,7 @@ design -save read hierarchy -top latchp proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_ecp5 +synth_ecp5 -latches info cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LUT4 @@ -15,7 +15,7 @@ design -load read hierarchy -top latchn proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_ecp5 +synth_ecp5 -latches info cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LUT4 @@ -26,7 +26,7 @@ design -load read hierarchy -top latchsr proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_ecp5 +synth_ecp5 -latches info cd latchsr # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 select -assert-count 1 t:PFUMX diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys index 4daf04050..404dc01dd 100644 --- a/tests/arch/ecp5/latches_abc9.ys +++ b/tests/arch/ecp5/latches_abc9.ys @@ -8,6 +8,6 @@ assign q = ~l; endmodule EOT # Can't run any sort of equivalence check because latches are blown to LUTs -synth_ecp5 -abc9 +synth_ecp5 -abc9 -latches info select -assert-count 2 t:LUT4 select -assert-none t:LUT4 %% t:* %D diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys index 1b1c00023..4ac60a8d7 100644 --- a/tests/arch/efinix/latches.ys +++ b/tests/arch/efinix/latches.ys @@ -4,7 +4,7 @@ design -save read hierarchy -top latchp proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix +synth_efinix -latches info cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_LUT4 @@ -15,7 +15,7 @@ design -load read hierarchy -top latchn proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix +synth_efinix -latches info cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_LUT4 @@ -26,7 +26,7 @@ design -load read hierarchy -top latchsr proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix +synth_efinix -latches info cd latchsr # Constrain all select calls below inside the top module select -assert-count 2 t:EFX_LUT4 diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys index b06dd630b..91c9df2b4 100644 --- a/tests/arch/ice40/latches.ys +++ b/tests/arch/ice40/latches.ys @@ -4,7 +4,7 @@ design -save read hierarchy -top latchp proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_ice40 +synth_ice40 -latches info cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:SB_LUT4 @@ -15,7 +15,7 @@ design -load read hierarchy -top latchn proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_ice40 +synth_ice40 -latches info cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:SB_LUT4 @@ -26,7 +26,7 @@ design -load read hierarchy -top latchsr proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_ice40 +synth_ice40 -latches info cd latchsr # Constrain all select calls below inside the top module select -assert-count 2 t:SB_LUT4 diff --git a/tests/arch/nanoxplore/latches.ys b/tests/arch/nanoxplore/latches.ys index b2eccfd80..270213d32 100644 --- a/tests/arch/nanoxplore/latches.ys +++ b/tests/arch/nanoxplore/latches.ys @@ -4,7 +4,7 @@ design -save read hierarchy -top latchp proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_nanoxplore -noiopad +synth_nanoxplore -noiopad -latches info cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:NX_LUT @@ -15,7 +15,7 @@ design -load read hierarchy -top latchn proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_nanoxplore -noiopad +synth_nanoxplore -noiopad -latches info cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:NX_LUT @@ -26,7 +26,7 @@ design -load read hierarchy -top latchsr proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_nanoxplore -noiopad +synth_nanoxplore -noiopad -latches info cd latchsr # Constrain all select calls below inside the top module select -assert-count 2 t:NX_LUT diff --git a/tests/arch/quicklogic/pp3/latches.ys b/tests/arch/quicklogic/pp3/latches.ys index 90a4f515b..3ae61b90f 100644 --- a/tests/arch/quicklogic/pp3/latches.ys +++ b/tests/arch/quicklogic/pp3/latches.ys @@ -4,7 +4,7 @@ design -save read hierarchy -top latchp proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_quicklogic +synth_quicklogic -latches info cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 select -assert-count 3 t:inpad @@ -17,7 +17,7 @@ design -load read hierarchy -top latchn proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_quicklogic +synth_quicklogic -latches info cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 select -assert-count 3 t:inpad @@ -30,7 +30,7 @@ design -load read hierarchy -top latchsr proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_quicklogic +synth_quicklogic -latches info cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LUT2 select -assert-count 1 t:LUT4 diff --git a/tests/proc/proc_latches.ys b/tests/proc/proc_latches.ys new file mode 100644 index 000000000..91749b6a7 --- /dev/null +++ b/tests/proc/proc_latches.ys @@ -0,0 +1,32 @@ +# warn +read_verilog <