diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index ae02a35ba..73aed8eae 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -118,6 +118,8 @@ struct RTLIL::SigNormIndex
 				xlog("\t%s = %s\n", module->design->twines.str(port).c_str(), log_signal(sig));
 				if (cell->port_dir(port) == RTLIL::PD_INPUT)
 					continue;
+				if (GetSize(sig) == 0)
+					continue;
 				xlog("%s is not an input in design %p\n", module->design->twines.str(port).c_str(), module->design);
 				if (sig.is_wire()) {
 					Wire * wire = sig.as_wire();