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Merge branch 'YosysHQ:main' into master

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Eder Monteiro 2025-07-07 11:38:22 -03:00 • committed by GitHub
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26 changed files with 948 additions and 78 deletions
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2
.github/workflows/extra-builds.yml vendored
View file

@ -36,7 +36,7 @@ jobs:
vs-build:
name: Visual Studio build
runs-on: windows-2019
runs-on: windows-latest
needs: [vs-prep, pre_job]
if: needs.pre_job.outputs.should_skip != 'true'
steps:

12
.github/workflows/test-build.yml vendored
View file

@ -40,6 +40,7 @@ jobs:
strategy:
matrix:
os: [ubuntu-latest, macos-latest]
sanitizer: [undefined, address]
fail-fast: false
steps:
- name: Checkout Yosys
@ -57,7 +58,7 @@ jobs:
mkdir build
cd build
make -f ../Makefile config-$CC
echo 'SANITIZER = undefined' >> Makefile.conf
echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf
make -f ../Makefile -j$procs ENABLE_LTO=1
- name: Log yosys-config output
@ -73,7 +74,7 @@ jobs:
- name: Store build artifact
uses: actions/upload-artifact@v4
with:
name: build-${{ matrix.os }}
name: build-${{ matrix.os }}-${{ matrix.sanitizer }}
path: build.tar
retention-days: 1
@ -84,10 +85,12 @@ jobs:
if: needs.pre_job.outputs.should_skip != 'true'
env:
CC: clang
ASAN_OPTIONS: halt_on_error=1
UBSAN_OPTIONS: halt_on_error=1
strategy:
matrix:
os: [ubuntu-latest, macos-latest]
sanitizer: [undefined, address]
fail-fast: false
steps:
- name: Checkout Yosys
@ -136,7 +139,7 @@ jobs:
- name: Download build artifact
uses: actions/download-artifact@v4
with:
name: build-${{ matrix.os }}
name: build-${{ matrix.os }}-${{ matrix.sanitizer }}
- name: Uncompress build
shell: bash
@ -168,6 +171,7 @@ jobs:
strategy:
matrix:
os: [ubuntu-latest]
sanitizer: [undefined, address]
fail-fast: false
steps:
- name: Checkout Yosys
@ -181,7 +185,7 @@ jobs:
- name: Download build artifact
uses: actions/download-artifact@v4
with:
name: build-${{ matrix.os }}
name: build-${{ matrix.os }}-${{ matrix.sanitizer }}
- name: Uncompress build
shell: bash

9
CHANGELOG
View file

@ -2,9 +2,16 @@
List of major changes and improvements between releases
=======================================================
Yosys 0.54 .. Yosys 0.55-dev
Yosys 0.55 .. Yosys 0.56-dev
--------------------------
Yosys 0.54 .. Yosys 0.55
--------------------------
* Various
- read_verilog: Implemented SystemVerilog unique/priority if.
- "attrmap" pass is able to alter memory attributes.
- verific: Support SVA followed-by operator in cover mode.
Yosys 0.53 .. Yosys 0.54
--------------------------
* New commands and options

4
Makefile
View file

@ -160,7 +160,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
YOSYS_VER := 0.54+0
YOSYS_VER := 0.55+0
YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)
@ -183,7 +183,7 @@ endif
OBJS = kernel/version_$(GIT_REV).o
bumpversion:
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 60f126c.. | wc -l`/;" Makefile
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)

4
docs/source/cell/word_mux.rst
View file

@ -24,8 +24,8 @@ are zero, the value from ``A`` input is sent to the output. If the :math:`n`\
'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of
the ``B`` input is sent to the output. When more than one bit from ``S`` is set
the output is undefined. Cells of this type are used to model "parallel cases"
(defined by using the ``parallel_case`` attribute or detected by an
optimization).
(defined by using the ``parallel_case`` attribute, the ``unique`` or ``unique0``
SystemVerilog keywords, or detected by an optimization).
The `$tribuf` cell is used to implement tristate logic. Cells of this type have
a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A``

2
docs/source/conf.py
View file

@ -6,7 +6,7 @@ import os
project = 'YosysHQ Yosys'
author = 'YosysHQ GmbH'
copyright ='2025 YosysHQ GmbH'
yosys_ver = "0.54"
yosys_ver = "0.55"
# select HTML theme
html_theme = 'furo-ys'

8
docs/source/yosys_internals/verilog.rst
View file

@ -377,7 +377,7 @@ from SystemVerilog:
- Assignments within expressions are supported.
- The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
accepted on ``if`` and ``case`` conditionals. (Those keywords are currently
handled in the same way as their equivalent ``full_case`` and
``parallel_case`` attributes on ``case`` statements, and checked
for syntactic validity but otherwise ignored on ``if`` statements.)
supported on ``if`` and ``case`` conditionals. (The Verilog frontend
will process conditionals using these keywords by annotating their
representation with the appropriate ``full_case`` and/or ``parallel_case``
attributes, which are described above.)

2
frontends/verific/verific.cc
View file

@ -3465,11 +3465,13 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
RuntimeFlags::SetVar("veri_replace_const_exprs", 1);
#endif
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
RuntimeFlags::SetVar("vhdl_replace_const_exprs", 1);
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);

7
frontends/verific/verificsva.cc
View file

@ -1613,7 +1613,10 @@ struct VerificSvaImporter
}
else
if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION ||
(mode_cover && (
inst->Type() == PRIM_SVA_OVERLAPPED_FOLLOWED_BY ||
inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)))
{
Net *antecedent_net = inst->GetInput1();
Net *consequent_net = inst->GetInput2();
@ -1621,7 +1624,7 @@ struct VerificSvaImporter
SvaFsm antecedent_fsm(clocking, trig);
node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net);
if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) {
if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || inst->Type() == PRIM_SVA_NON_OVERLAPPED_FOLLOWED_BY) {
int next_node = antecedent_fsm.createNode();
antecedent_fsm.createEdge(node, next_node);
node = next_node;

2
frontends/verilog/verilog_frontend.cc
View file

@ -753,7 +753,7 @@ struct VerilogFileList : public Pass {
break;
}
extra_args(args, argidx, design);
extra_args(args, argidx, design, false);
}
} VerilogFilelist;

3
frontends/verilog/verilog_lexer.l
View file

@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s
}
\" { BEGIN(STRING); }
<STRING>\\. { yymore(); real_location = old_location; }
<STRING>([^\\"]|\\.)+ { yymore(); real_location = old_location; }
<STRING>\" {
BEGIN(0);
char *yystr = strdup(yytext);
@ -376,7 +376,6 @@ TIME_SCALE_SUFFIX [munpf]?s
free(yystr);
return TOK_STRING;
}
<STRING>. { yymore(); real_location = old_location; }
and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
yylval->string = new std::string(yytext);

47
frontends/verilog/verilog_parser.y
View file

@ -2873,16 +2873,37 @@ behavioral_stmt:
ast_stack.pop_back();
} |
if_attr TOK_IF '(' expr ')' {
AstNode *node = new AstNode(AST_CASE);
AstNode *node = 0;
AstNode *block = new AstNode(AST_BLOCK);
AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
AstNode *context = ast_stack.back();
if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) {
AstNode *outer = ast_stack[ast_stack.size() - 2];
log_assert (outer && outer->type == AST_CASE);
if (outer->get_bool_attribute(ID::parallel_case)) {
// parallel "else if": append condition to outer "if"
node = outer;
log_assert (node->children.size());
ast_stack.pop_back();
delete node->children.back();
node->children.pop_back();
ast_stack.push_back(block);
} else if (outer->get_bool_attribute(ID::full_case))
(*$1)[ID::full_case] = AstNode::mkconst_int(1, false);
}
AstNode *expr = new AstNode(AST_REDUCE_BOOL, $4);
if (!node) {
// not parallel "else if": begin new construction
node = new AstNode(AST_CASE);
append_attr(node, $1);
ast_stack.back()->children.push_back(node);
node->children.push_back(node->get_bool_attribute(ID::parallel_case) ? AstNode::mkconst_int(1, false, 1) : expr);
} else
free_attr($1);
AstNode *cond = new AstNode(AST_COND, node->get_bool_attribute(ID::parallel_case) ? expr : AstNode::mkconst_int(1, false, 1), block);
SET_AST_NODE_LOC(cond, @4, @4);
ast_stack.back()->children.push_back(node);
node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
node->children.push_back(cond);
ast_stack.push_back(node);
ast_stack.push_back(block);
append_attr(node, $1);
} behavioral_stmt {
SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
} optional_else {
@ -2908,21 +2929,25 @@ if_attr:
} |
attr TOK_UNIQUE0 {
AstNode *context = ast_stack.back();
if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) )
if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if))
frontend_verilog_yyerror("unique0 keyword cannot be used for 'else if' branch.");
$$ = $1; // accept unique0 keyword, but ignore it for now
(*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
$$ = $1;
} |
attr TOK_PRIORITY {
AstNode *context = ast_stack.back();
if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) )
if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if))
frontend_verilog_yyerror("priority keyword cannot be used for 'else if' branch.");
$$ = $1; // accept priority keyword, but ignore it for now
(*$1)[ID::full_case] = AstNode::mkconst_int(1, false);
$$ = $1;
} |
attr TOK_UNIQUE {
AstNode *context = ast_stack.back();
if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) )
if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if))
frontend_verilog_yyerror("unique keyword cannot be used for 'else if' branch.");
$$ = $1; // accept unique keyword, but ignore it for now
(*$1)[ID::full_case] = AstNode::mkconst_int(1, false);
(*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
$$ = $1;
};
case_attr:

1
kernel/driver.cc
View file

@ -20,6 +20,7 @@
#include "kernel/yosys.h"
#include "kernel/hashlib.h"
#include "libs/sha1/sha1.h"
#define CXXOPTS_VECTOR_DELIMITER '\0'
#include "libs/cxxopts/include/cxxopts.hpp"
#include <iostream>

5
kernel/yosys.cc
View file

@ -187,12 +187,14 @@ int run_command(const std::string &command, std::function<void(const std::string
#endif
bool already_setup = false;
bool already_shutdown = false;
void yosys_setup()
{
if(already_setup)
return;
already_setup = true;
already_shutdown = false;
#ifdef WITH_PYTHON
// With Python 3.12, calling PyImport_AppendInittab on an already
@ -224,12 +226,11 @@ bool yosys_already_setup()
return already_setup;
}
bool already_shutdown = false;
void yosys_shutdown()
{
if(already_shutdown)
return;
already_setup = false;
already_shutdown = true;
log_pop();

6
passes/cmds/splitnets.cc
View file

@ -207,8 +207,12 @@ struct SplitnetsPass : public Pass {
else
{
for (auto wire : module->wires()) {
if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
if (((wire->width > 1) || (wire->has_attribute(ID::single_bit_vector)))
&& (wire->port_id == 0 || flag_ports)
&& design->selected(module, wire)) {
wire->attributes.erase(ID::single_bit_vector);
worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
}
}
for (auto &it : worker.splitmap)

14
passes/opt/opt_dff.cc
View file

@ -738,7 +738,11 @@ struct OptDffWorker
ModWalker modwalker(module->design, module);
QuickConeSat qcsat(modwalker);
// Run as a separate sub-pass, so that we don't mutate (non-FF) cells under ModWalker.
// Defer mutating cells by removing them/emiting new flip flops so that
// cell references in modwalker are not invalidated
std::vector<RTLIL::Cell*> cells_to_remove;
std::vector<FfData> ffs_to_emit;
bool did_something = false;
for (auto cell : module->selected_cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
@ -830,16 +834,20 @@ struct OptDffWorker
if (!removed_sigbits.count(i))
keep_bits.push_back(i);
if (keep_bits.empty()) {
module->remove(cell);
cells_to_remove.emplace_back(cell);
did_something = true;
continue;
}
ff = ff.slice(keep_bits);
ff.cell = cell;
ff.emit();
ffs_to_emit.emplace_back(ff);
did_something = true;
}
}
for (auto* cell : cells_to_remove)
module->remove(cell);
for (auto& ff : ffs_to_emit)
ff.emit();
return did_something;
}
};

24
passes/techmap/attrmap.cc
View file

@ -263,33 +263,27 @@ struct AttrmapPass : public Pass {
if (modattr_mode)
{
for (auto module : design->selected_whole_modules())
for (auto module : design->all_selected_whole_modules())
attrmap_apply(stringf("%s", log_id(module)), actions, module->attributes);
}
else
{
for (auto module : design->selected_modules())
for (auto module : design->all_selected_modules())
{
for (auto wire : module->selected_wires())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(wire)), actions, wire->attributes);
for (auto memb : module->selected_members())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(memb)), actions, memb->attributes);
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes);
for (auto proc : module->processes)
// attrmap already applied to process itself during above loop, but not its children
for (auto proc : module->selected_processes())
{
if (!design->selected(module, proc.second))
continue;
attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes);
std::vector<RTLIL::CaseRule*> all_cases = {&proc.second->root_case};
std::vector<RTLIL::CaseRule*> all_cases = {&proc->root_case};
while (!all_cases.empty()) {
RTLIL::CaseRule *cs = all_cases.back();
all_cases.pop_back();
attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes);
attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc)), actions, cs->attributes);
for (auto &sw : cs->switches) {
attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes);
attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc)), actions, sw->attributes);
all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end());
}
}

10
techlibs/gowin/cells_xtra.py
View file

@ -11,6 +11,7 @@ import re
class State(Enum):
OUTSIDE = auto()
IN_MODULE = auto()
IN_MODULE_MULTILINE = auto()
IN_PARAMETER = auto()
_skip = { # These are already described, no need to extract them from the vendor files
@ -47,12 +48,20 @@ def xtract_cells_decl(dir, fout):
fout.write(l)
if l[-1] != '\n':
fout.write('\n')
if l.rstrip()[-1] != ';':
state = State.IN_MODULE_MULTILINE
elif l.startswith('parameter') and state == State.IN_MODULE:
fout.write(l)
if l.rstrip()[-1] == ',':
state = State.IN_PARAMETER
if l[-1] != '\n':
fout.write('\n')
elif l and state == State.IN_MODULE_MULTILINE:
fout.write(l)
if l[-1] != '\n':
fout.write('\n')
if l.rstrip()[-1] == ';':
state = State.IN_MODULE
elif state == State.IN_PARAMETER:
fout.write(l)
if l.rstrip()[-1] == ';':
@ -65,6 +74,7 @@ def xtract_cells_decl(dir, fout):
if l[-1] != '\n':
fout.write('\n')
if __name__ == '__main__':
parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.')
parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/')

601
techlibs/gowin/cells_xtra_gw5a.v
View file

@ -80,19 +80,8 @@ endmodule
module MIPI_OBUF_A (...);
output O, OB;
input I, IB, IL, MODESEL;
endmodule
module IBUF_R (...);
input I;
input RTEN;
output O;
endmodule
module IOBUF_R (...);
input I,OEN;
input RTEN;
output O;
inout IO;
inout IO, IOB;
input OEN, OENB;
endmodule
module ELVDS_IOBUF_R (...);
@ -113,6 +102,21 @@ input I, IB;
input ADCEN;
endmodule
module MIPI_CPHY_IBUF (...);
output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2;
inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
input I0, IB0, I1, IB1, I2, IB2;
input OEN, OENB;
input HSEN;
endmodule
module MIPI_CPHY_OBUF (...);
output O0, OB0, O1, OB1, O2, OB2;
input I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2;
inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
input OEN, OENB, MODESEL, VCOME;
endmodule
module SDPB (...);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
@ -598,8 +602,8 @@ endmodule
module SDP36KE (...);
parameter ECC_WRITE_EN="FALSE";
parameter ECC_READ_EN="FALSE";
parameter ECC_WRITE_EN="TRUE";
parameter ECC_READ_EN="TRUE";
parameter READ_MODE = 1'b0;
parameter BLK_SEL_A = 3'b000;
parameter BLK_SEL_B = 3'b000;
@ -764,6 +768,14 @@ output [7:0] ECCP;
endmodule
module SDP136K (...);
input CLKA, CLKB;
input WE, RE;
input [10:0] ADA, ADB;
input [67:0] DI;
output [67:0] DO;
endmodule
module MULTADDALU12X12 (...);
parameter A0REG_CLK = "BYPASS";
parameter A0REG_CE = "CE0";
@ -980,6 +992,24 @@ input PSEL;
input PADDSUB;
endmodule
module MULTACC (...);
output [23:0] DATAO, CASO;
input CE, CLK;
input [5:0] COFFIN0, COFFIN1, COFFIN2;
input [9:0] DATAIN0, DATAIN1;
input [9:0] DATAIN2;
input RSTN;
input [23:0] CASI;
parameter COFFIN_WIDTH = 4;
parameter DATAIN_WIDTH = 8;
parameter IREG = 1'b0;
parameter OREG = 1'b0;
parameter PREG = 1'b0;
parameter ACC_EN = "FALSE";
parameter CASI_EN = "FALSE";
parameter CASO_EN = "FALSE";
endmodule
module IDDR_MEM (...);
input D, ICLK, PCLK;
input [2:0] WADDR;
@ -1048,6 +1078,12 @@ output Q0, Q1;
endmodule
module OSER14 (...);
input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13;
input PCLK, FCLK, RESET;
output Q;
endmodule
module IODELAY (...);
parameter C_STATIC_DLY = 0;
parameter DYN_DLY_EN = "FALSE";
@ -1066,13 +1102,39 @@ output [31:0] Q;
input D;
input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
input RESET;
output DF;
input SDTAP;
input VALUE;
input [7:0] DLYSTEP;
parameter C_STATIC_DLY = 0;
parameter DYN_DLY_EN = "FALSE";
parameter ADAPT_EN = "FALSE";
output DF0, DF1;
input SDTAP0, SDTAP1;
input VALUE0,VALUE1;
input [7:0] DLYSTEP0,DLYSTEP1;
parameter C_STATIC_DLY_0 = 0;
parameter DYN_DLY_EN_0 = "FALSE";
parameter ADAPT_EN_0 = "FALSE";
parameter C_STATIC_DLY_1 = 0;
parameter DYN_DLY_EN_1 = "FALSE";
parameter ADAPT_EN_1 = "FALSE";
endmodule
module OSIDES64 (...);
output [63:0] Q;
input D;
input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
input RESET;
output DF0, DF1, DF2, DF3;
input SDTAP0, SDTAP1, SDTAP2, SDTAP3;
input VALUE0, VALUE1, VALUE2, VALUE3;
input [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3;
parameter C_STATIC_DLY_0 = 0;
parameter DYN_DLY_EN_0 = "FALSE";
parameter ADAPT_EN_0 = "FALSE";
parameter C_STATIC_DLY_1 = 0;
parameter DYN_DLY_EN_1 = "FALSE";
parameter ADAPT_EN_1 = "FALSE";
parameter C_STATIC_DLY_2 = 0;
parameter DYN_DLY_EN_2 = "FALSE";
parameter ADAPT_EN_2 = "FALSE";
parameter C_STATIC_DLY_3 = 0;
parameter DYN_DLY_EN_3 = "FALSE";
parameter ADAPT_EN_3 = "FALSE";
endmodule
module DCE (...);
@ -1132,6 +1194,17 @@ output OSCOUT;
input OSCEN;
endmodule
module OSCB (...);
parameter FREQ_MODE = "25";
parameter FREQ_DIV = 10;
parameter DYN_TRIM_EN = "FALSE";
output OSCOUT;
output OSCREF;
input OSCEN, FMODE;
input [7:0] RTRIM;
input [5:0] RTCTRIM;
endmodule
module PLL (...);
input CLKIN;
input CLKFB;
@ -1571,8 +1644,8 @@ input ADWSEL;
endmodule
module OTP (...);
parameter MODE = 1'b0;
input READ, SHIFT;
parameter MODE = 2'b01;
input CLK, READ, SHIFT;
output DOUT;
endmodule
@ -1615,6 +1688,31 @@ input ERR0INJECT,ERR1INJECT;
input [6:0] ERRINJ0LOC,ERRINJ1LOC;
endmodule
module CMSERB (...);
output RUNNING;
output CRCERR;
output CRCDONE;
output ECCCORR;
output ECCUNCORR;
output [12:0] ERRLOC;
output ECCDEC;
output DSRRD;
output DSRWR;
output ASRRESET;
output ASRINC;
output REFCLK;
input CLK;
input [2:0] SEREN;
input ERR0INJECT,ERR1INJECT;
input [6:0] ERRINJ0LOC,ERRINJ1LOC;
endmodule
module SAMBA (...);
parameter MODE = 2'b00;
input SPIAD;
input LOAD;
endmodule
module ADCLRC (...);
endmodule
@ -1624,6 +1722,12 @@ endmodule
module ADC (...);
endmodule
module ADC_SAR (...);
endmodule
module LICD (...);
endmodule
module MIPI_DPHY (...);
output RX_CLK_O, TX_CLK_O;
output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
@ -1632,6 +1736,7 @@ input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;
output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;
inout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;
input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK,
LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK;
input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;
input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;
input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;
@ -1639,6 +1744,8 @@ input HSTXD_VLD;
input CK0, CK90, CK180, CK270;
input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;
input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK,
HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK,
LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;
input RX_DRST_N, TX_DRST_N, WALIGN_DVLD;
output [7:0] MRDATA;
input MA_INC, MCLK;
@ -1714,7 +1821,7 @@ parameter RX_RD_START_DEPTH = 5'b00001;
parameter RX_SYNC_MODE = 1'b0 ;
parameter RX_WORD_ALIGN_BYPASS = 1'b0 ;
parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ;
parameter RX_WORD_LITTLE_ENDIAN = 1'b0 ;
parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ;
parameter TX_BYPASS_MODE = 1'b0 ;
parameter TX_BYTECLK_SYNC_MODE = 1'b0 ;
parameter TX_OCLK_USE_CIBCLK = 1'b0 ;
@ -1917,6 +2024,437 @@ parameter TEST_P_IMP_LN3 = 1'b0 ;
parameter TEST_P_IMP_LNCK = 1'b0 ;
endmodule
module MIPI_DPHYA (...);
output RX_CLK_O, TX_CLK_O;
output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;
output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;
inout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;
input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK,
LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK;
input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;
input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;
input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;
input HSTXD_VLD;
input CK0, CK90, CK180, CK270;
input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;
input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK,
HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK,
LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;
input RX_DRST_N, TX_DRST_N, WALIGN_DVLD;
output [7:0] MRDATA;
input MA_INC, MCLK;
input [1:0] MOPCODE;
input [7:0] MWDATA;
input SPLL_CKN, SPLL_CKP;
output ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;
output D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;
output D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;
input D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;
input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;
input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;
input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;
input ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;
parameter TX_PLLCLK = "NONE";
parameter RX_ALIGN_BYTE = 8'b10111000 ;
parameter RX_HS_8BIT_MODE = 1'b0 ;
parameter RX_LANE_ALIGN_EN = 1'b0 ;
parameter TX_HS_8BIT_MODE = 1'b0 ;
parameter HSREG_EN_LN0 = 1'b0;
parameter HSREG_EN_LN1 = 1'b0;
parameter HSREG_EN_LN2 = 1'b0;
parameter HSREG_EN_LN3 = 1'b0;
parameter HSREG_EN_LNCK = 1'b0;
parameter LANE_DIV_SEL = 2'b00;
parameter HSRX_EN = 1'b1 ;
parameter HSRX_LANESEL = 4'b1111 ;
parameter HSRX_LANESEL_CK = 1'b1 ;
parameter HSTX_EN_LN0 = 1'b0 ;
parameter HSTX_EN_LN1 = 1'b0 ;
parameter HSTX_EN_LN2 = 1'b0 ;
parameter HSTX_EN_LN3 = 1'b0 ;
parameter HSTX_EN_LNCK = 1'b0 ;
parameter LPTX_EN_LN0 = 1'b1 ;
parameter LPTX_EN_LN1 = 1'b1 ;
parameter LPTX_EN_LN2 = 1'b1 ;
parameter LPTX_EN_LN3 = 1'b1 ;
parameter LPTX_EN_LNCK = 1'b1 ;
parameter TXDP_EN_LN0 = 1'b0 ;
parameter TXDP_EN_LN1 = 1'b0 ;
parameter TXDP_EN_LN2 = 1'b0 ;
parameter TXDP_EN_LN3 = 1'b0 ;
parameter TXDP_EN_LNCK = 1'b0 ;
parameter SPLL_DIV_SEL = 2'b00;
parameter DPHY_CK_SEL = 2'b01;
parameter CKLN_DELAY_EN = 1'b0;
parameter CKLN_DELAY_OVR_VAL = 7'b0000000;
parameter D0LN_DELAY_EN = 1'b0;
parameter D0LN_DELAY_OVR_VAL = 7'b0000000;
parameter D0LN_DESKEW_BYPASS = 1'b0;
parameter D1LN_DELAY_EN = 1'b0;
parameter D1LN_DELAY_OVR_VAL = 7'b0000000;
parameter D1LN_DESKEW_BYPASS = 1'b0;
parameter D2LN_DELAY_EN = 1'b0;
parameter D2LN_DELAY_OVR_VAL = 7'b0000000;
parameter D2LN_DESKEW_BYPASS = 1'b0;
parameter D3LN_DELAY_EN = 1'b0;
parameter D3LN_DELAY_OVR_VAL = 7'b0000000;
parameter D3LN_DESKEW_BYPASS = 1'b0;
parameter DESKEW_EN_LOW_DELAY = 1'b0;
parameter DESKEW_EN_ONE_EDGE = 1'b0;
parameter DESKEW_FAST_LOOP_TIME = 4'b0000;
parameter DESKEW_FAST_MODE = 1'b0;
parameter DESKEW_HALF_OPENING = 6'b010110;
parameter DESKEW_LSB_MODE = 2'b00;
parameter DESKEW_M = 3'b011;
parameter DESKEW_M_TH = 13'b0000110100110;
parameter DESKEW_MAX_SETTING = 7'b0100001;
parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ;
parameter DESKEW_RST_BYPASS = 1'b0 ;
parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ;
parameter RX_CLK_1X_SYNC_SEL = 1'b0 ;
parameter RX_INVERT = 1'b0 ;
parameter RX_ONE_BYTE0_MATCH = 1'b0 ;
parameter RX_RD_START_DEPTH = 5'b00001;
parameter RX_SYNC_MODE = 1'b0 ;
parameter RX_WORD_ALIGN_BYPASS = 1'b0 ;
parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ;
parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ;
parameter TX_BYPASS_MODE = 1'b0 ;
parameter TX_BYTECLK_SYNC_MODE = 1'b0 ;
parameter TX_OCLK_USE_CIBCLK = 1'b0 ;
parameter TX_RD_START_DEPTH = 5'b00001;
parameter TX_SYNC_MODE = 1'b0 ;
parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ;
parameter EQ_CS_LANE0 = 3'b100;
parameter EQ_CS_LANE1 = 3'b100;
parameter EQ_CS_LANE2 = 3'b100;
parameter EQ_CS_LANE3 = 3'b100;
parameter EQ_CS_LANECK = 3'b100;
parameter EQ_RS_LANE0 = 3'b100;
parameter EQ_RS_LANE1 = 3'b100;
parameter EQ_RS_LANE2 = 3'b100;
parameter EQ_RS_LANE3 = 3'b100;
parameter EQ_RS_LANECK = 3'b100;
parameter HSCLK_LANE_LN0 = 1'b0;
parameter HSCLK_LANE_LN1 = 1'b0;
parameter HSCLK_LANE_LN2 = 1'b0;
parameter HSCLK_LANE_LN3 = 1'b0;
parameter HSCLK_LANE_LNCK = 1'b1;
parameter ALP_ED_EN_LANE0 = 1'b1 ;
parameter ALP_ED_EN_LANE1 = 1'b1 ;
parameter ALP_ED_EN_LANE2 = 1'b1 ;
parameter ALP_ED_EN_LANE3 = 1'b1 ;
parameter ALP_ED_EN_LANECK = 1'b1 ;
parameter ALP_ED_TST_LANE0 = 1'b0 ;
parameter ALP_ED_TST_LANE1 = 1'b0 ;
parameter ALP_ED_TST_LANE2 = 1'b0 ;
parameter ALP_ED_TST_LANE3 = 1'b0 ;
parameter ALP_ED_TST_LANECK = 1'b0 ;
parameter ALP_EN_LN0 = 1'b0 ;
parameter ALP_EN_LN1 = 1'b0 ;
parameter ALP_EN_LN2 = 1'b0 ;
parameter ALP_EN_LN3 = 1'b0 ;
parameter ALP_EN_LNCK = 1'b0 ;
parameter ALP_HYS_EN_LANE0 = 1'b1 ;
parameter ALP_HYS_EN_LANE1 = 1'b1 ;
parameter ALP_HYS_EN_LANE2 = 1'b1 ;
parameter ALP_HYS_EN_LANE3 = 1'b1 ;
parameter ALP_HYS_EN_LANECK = 1'b1 ;
parameter ALP_TH_LANE0 = 4'b1000 ;
parameter ALP_TH_LANE1 = 4'b1000 ;
parameter ALP_TH_LANE2 = 4'b1000 ;
parameter ALP_TH_LANE3 = 4'b1000 ;
parameter ALP_TH_LANECK = 4'b1000 ;
parameter ANA_BYTECLK_PH = 2'b00 ;
parameter BIT_REVERSE_LN0 = 1'b0 ;
parameter BIT_REVERSE_LN1 = 1'b0 ;
parameter BIT_REVERSE_LN2 = 1'b0 ;
parameter BIT_REVERSE_LN3 = 1'b0 ;
parameter BIT_REVERSE_LNCK = 1'b0 ;
parameter BYPASS_TXHCLKEN = 1'b1 ;
parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ;
parameter BYTE_CLK_POLAR = 1'b0 ;
parameter BYTE_REVERSE_LN0 = 1'b0 ;
parameter BYTE_REVERSE_LN1 = 1'b0 ;
parameter BYTE_REVERSE_LN2 = 1'b0 ;
parameter BYTE_REVERSE_LN3 = 1'b0 ;
parameter BYTE_REVERSE_LNCK = 1'b0 ;
parameter EN_CLKB1X = 1'b1 ;
parameter EQ_PBIAS_LANE0 = 4'b1000 ;
parameter EQ_PBIAS_LANE1 = 4'b1000 ;
parameter EQ_PBIAS_LANE2 = 4'b1000 ;
parameter EQ_PBIAS_LANE3 = 4'b1000 ;
parameter EQ_PBIAS_LANECK = 4'b1000 ;
parameter EQ_ZLD_LANE0 = 4'b1000 ;
parameter EQ_ZLD_LANE1 = 4'b1000 ;
parameter EQ_ZLD_LANE2 = 4'b1000 ;
parameter EQ_ZLD_LANE3 = 4'b1000 ;
parameter EQ_ZLD_LANECK = 4'b1000 ;
parameter HIGH_BW_LANE0 = 1'b1 ;
parameter HIGH_BW_LANE1 = 1'b1 ;
parameter HIGH_BW_LANE2 = 1'b1 ;
parameter HIGH_BW_LANE3 = 1'b1 ;
parameter HIGH_BW_LANECK = 1'b1 ;
parameter HSREG_VREF_CTL = 3'b100 ;
parameter HSREG_VREF_EN = 1'b1 ;
parameter HSRX_DLY_CTL_CK = 7'b0000000 ;
parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ;
parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ;
parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ;
parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ;
parameter HSRX_DLY_SEL_LANE0 = 1'b0 ;
parameter HSRX_DLY_SEL_LANE1 = 1'b0 ;
parameter HSRX_DLY_SEL_LANE2 = 1'b0 ;
parameter HSRX_DLY_SEL_LANE3 = 1'b0 ;
parameter HSRX_DLY_SEL_LANECK = 1'b0 ;
parameter HSRX_DUTY_LANE0 = 4'b1000 ;
parameter HSRX_DUTY_LANE1 = 4'b1000 ;
parameter HSRX_DUTY_LANE2 = 4'b1000 ;
parameter HSRX_DUTY_LANE3 = 4'b1000 ;
parameter HSRX_DUTY_LANECK = 4'b1000 ;
parameter HSRX_EQ_EN_LANE0 = 1'b1 ;
parameter HSRX_EQ_EN_LANE1 = 1'b1 ;
parameter HSRX_EQ_EN_LANE2 = 1'b1 ;
parameter HSRX_EQ_EN_LANE3 = 1'b1 ;
parameter HSRX_EQ_EN_LANECK = 1'b1 ;
parameter HSRX_IBIAS = 4'b0011 ;
parameter HSRX_IBIAS_TEST_EN = 1'b0 ;
parameter HSRX_IMARG_EN = 1'b0 ;
parameter HSRX_ODT_EN = 1'b1 ;
parameter HSRX_ODT_TST = 4'b0000 ;
parameter HSRX_ODT_TST_CK = 1'b0 ;
parameter HSRX_SEL = 4'b0000 ;
parameter HSRX_STOP_EN = 1'b0 ;
parameter HSRX_TST = 4'b0000 ;
parameter HSRX_TST_CK = 1'b0 ;
parameter HSRX_WAIT4EDGE = 1'b1 ;
parameter HYST_NCTL = 2'b01 ;
parameter HYST_PCTL = 2'b01 ;
parameter IBIAS_TEST_EN = 1'b0 ;
parameter LB_CH_SEL = 1'b0 ;
parameter LB_EN_LN0 = 1'b0 ;
parameter LB_EN_LN1 = 1'b0 ;
parameter LB_EN_LN2 = 1'b0 ;
parameter LB_EN_LN3 = 1'b0 ;
parameter LB_EN_LNCK = 1'b0 ;
parameter LB_POLAR_LN0 = 1'b0 ;
parameter LB_POLAR_LN1 = 1'b0 ;
parameter LB_POLAR_LN2 = 1'b0 ;
parameter LB_POLAR_LN3 = 1'b0 ;
parameter LB_POLAR_LNCK = 1'b0 ;
parameter LOW_LPRX_VTH = 1'b0 ;
parameter LPBK_DATA2TO1 = 4'b0000;
parameter LPBK_DATA2TO1_CK = 1'b0 ;
parameter LPBK_EN = 1'b0 ;
parameter LPBK_SEL = 4'b0000;
parameter LPBKTST_EN = 4'b0000;
parameter LPBKTST_EN_CK = 1'b0 ;
parameter LPRX_EN = 1'b1 ;
parameter LPRX_TST = 4'b0000;
parameter LPRX_TST_CK = 1'b0 ;
parameter LPTX_DAT_POLAR_LN0 = 1'b0 ;
parameter LPTX_DAT_POLAR_LN1 = 1'b0 ;
parameter LPTX_DAT_POLAR_LN2 = 1'b0 ;
parameter LPTX_DAT_POLAR_LN3 = 1'b0 ;
parameter LPTX_DAT_POLAR_LNCK = 1'b0 ;
parameter LPTX_NIMP_LN0 = 3'b100 ;
parameter LPTX_NIMP_LN1 = 3'b100 ;
parameter LPTX_NIMP_LN2 = 3'b100 ;
parameter LPTX_NIMP_LN3 = 3'b100 ;
parameter LPTX_NIMP_LNCK = 3'b100 ;
parameter LPTX_PIMP_LN0 = 3'b100 ;
parameter LPTX_PIMP_LN1 = 3'b100 ;
parameter LPTX_PIMP_LN2 = 3'b100 ;
parameter LPTX_PIMP_LN3 = 3'b100 ;
parameter LPTX_PIMP_LNCK = 3'b100 ;
parameter MIPI_PMA_DIS_N = 1'b1 ;
parameter PGA_BIAS_LANE0 = 4'b1000 ;
parameter PGA_BIAS_LANE1 = 4'b1000 ;
parameter PGA_BIAS_LANE2 = 4'b1000 ;
parameter PGA_BIAS_LANE3 = 4'b1000 ;
parameter PGA_BIAS_LANECK = 4'b1000 ;
parameter PGA_GAIN_LANE0 = 4'b1000 ;
parameter PGA_GAIN_LANE1 = 4'b1000 ;
parameter PGA_GAIN_LANE2 = 4'b1000 ;
parameter PGA_GAIN_LANE3 = 4'b1000 ;
parameter PGA_GAIN_LANECK = 4'b1000 ;
parameter RX_ODT_TRIM_LANE0 = 4'b1000 ;
parameter RX_ODT_TRIM_LANE1 = 4'b1000 ;
parameter RX_ODT_TRIM_LANE2 = 4'b1000 ;
parameter RX_ODT_TRIM_LANE3 = 4'b1000 ;
parameter RX_ODT_TRIM_LANECK = 4'b1000 ;
parameter SLEWN_CTL_LN0 = 4'b1111 ;
parameter SLEWN_CTL_LN1 = 4'b1111 ;
parameter SLEWN_CTL_LN2 = 4'b1111 ;
parameter SLEWN_CTL_LN3 = 4'b1111 ;
parameter SLEWN_CTL_LNCK = 4'b1111 ;
parameter SLEWP_CTL_LN0 = 4'b1111 ;
parameter SLEWP_CTL_LN1 = 4'b1111 ;
parameter SLEWP_CTL_LN2 = 4'b1111 ;
parameter SLEWP_CTL_LN3 = 4'b1111 ;
parameter SLEWP_CTL_LNCK = 4'b1111 ;
parameter STP_UNIT = 2'b01 ;
parameter TERMN_CTL_LN0 = 4'b1000 ;
parameter TERMN_CTL_LN1 = 4'b1000 ;
parameter TERMN_CTL_LN2 = 4'b1000 ;
parameter TERMN_CTL_LN3 = 4'b1000 ;
parameter TERMN_CTL_LNCK = 4'b1000 ;
parameter TERMP_CTL_LN0 = 4'b1000 ;
parameter TERMP_CTL_LN1 = 4'b1000 ;
parameter TERMP_CTL_LN2 = 4'b1000 ;
parameter TERMP_CTL_LN3 = 4'b1000 ;
parameter TERMP_CTL_LNCK = 4'b1000 ;
parameter TEST_EN_LN0 = 1'b0 ;
parameter TEST_EN_LN1 = 1'b0 ;
parameter TEST_EN_LN2 = 1'b0 ;
parameter TEST_EN_LN3 = 1'b0 ;
parameter TEST_EN_LNCK = 1'b0 ;
parameter TEST_N_IMP_LN0 = 1'b0 ;
parameter TEST_N_IMP_LN1 = 1'b0 ;
parameter TEST_N_IMP_LN2 = 1'b0 ;
parameter TEST_N_IMP_LN3 = 1'b0 ;
parameter TEST_N_IMP_LNCK = 1'b0 ;
parameter TEST_P_IMP_LN0 = 1'b0 ;
parameter TEST_P_IMP_LN1 = 1'b0 ;
parameter TEST_P_IMP_LN2 = 1'b0 ;
parameter TEST_P_IMP_LN3 = 1'b0 ;
parameter TEST_P_IMP_LNCK = 1'b0 ;
endmodule
module MIPI_CPHY (...);
output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD;
output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD;
output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD;
output D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR;
output [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA;
output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O;
output HSTX_FIFO_AE, HSTX_FIFO_AF;
output HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR;
output RX_CLK_MUXED;
output TX_CLK_1X_O;
output DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C;
output [7:0] MDRP_RDATA;
inout D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C;
input D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN;
input [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA;
input D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD;
input [1:0] D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS;
input D0LN_RX_CLK_1X_I,D1LN_RX_CLK_1X_I, D2LN_RX_CLK_1X_I;
input D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N;
input HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2;
input [7:0] MDRP_A_D_I;
input MDRP_A_INC_I;
input MDRP_CLK_I;
input [1:0] MDRP_OPCODE_I;
input PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX;
input ARST_RXLN0, ARST_RXLN1, ARST_RXLN2;
input ARSTN_TX;
input RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2;
input TX_CLK_1X_I;
input TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2;
input TXHCLK_EN;
input DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2;
input GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270;
input HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2;
input HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2;
input LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2;
input SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP;
parameter TX_PLLCLK = "NONE";
parameter D0LN_HS_TX_EN = 1'b1;
parameter D1LN_HS_TX_EN = 1'b1;
parameter D2LN_HS_TX_EN = 1'b1;
parameter D0LN_HS_RX_EN = 1'b1;
parameter D1LN_HS_RX_EN = 1'b1;
parameter D2LN_HS_RX_EN = 1'b1;
parameter TX_HS_21BIT_MODE = 1'b0;
parameter RX_OUTCLK_SEL = 2'b00;
parameter TX_W_LENDIAN = 1'b1;
parameter CLK_SEL = 2'b00;
parameter LNDIV_RATIO = 4'b0000;
parameter LNDIV_EN = 1'b0;
parameter D0LN_TX_REASGN_A = 2'b00;
parameter D0LN_TX_REASGN_B = 2'b01;
parameter D0LN_TX_REASGN_C = 2'b10;
parameter D0LN_RX_HS_21BIT_MODE = 1'b0;
parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1;
parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001;
parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100;
parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1;
parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001;
parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100;
parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1;
parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001;
parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100;
parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0;
parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001;
parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100;
parameter D0LN_RX_W_LENDIAN = 1'b1;
parameter D0LN_RX_REASGN_A = 2'b00;
parameter D0LN_RX_REASGN_B = 2'b01;
parameter D0LN_RX_REASGN_C = 2'b10;
parameter HSRX_LNSEL = 3'b111;
parameter EQ_RS_LN0 = 3'b001;
parameter EQ_CS_LN0 = 3'b101;
parameter PGA_GAIN_LN0 = 4'b0110;
parameter PGA_BIAS_LN0 = 4'b1000;
parameter EQ_PBIAS_LN0 = 4'b0100;
parameter EQ_ZLD_LN0 = 4'b1000;
parameter D1LN_TX_REASGN_A = 2'b00;
parameter D1LN_TX_REASGN_B = 2'b01;
parameter D1LN_TX_REASGN_C = 2'b10;
parameter D1LN_RX_HS_21BIT_MODE = 1'b0;
parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1;
parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001;
parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100;
parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1;
parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001;
parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100;
parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1;
parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001;
parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100;
parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0;
parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001;
parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100;
parameter D1LN_RX_W_LENDIAN = 1'b1;
parameter D1LN_RX_REASGN_A = 2'b00;
parameter D1LN_RX_REASGN_B = 2'b01;
parameter D1LN_RX_REASGN_C = 2'b10;
parameter EQ_RS_LN1 = 3'b001;
parameter EQ_CS_LN1 = 3'b101;
parameter PGA_GAIN_LN1 = 4'b0110;
parameter PGA_BIAS_LN1 = 4'b1000;
parameter EQ_PBIAS_LN1 = 4'b0100;
parameter EQ_ZLD_LN1 = 4'b1000;
parameter D2LN_TX_REASGN_A = 2'b00;
parameter D2LN_TX_REASGN_B = 2'b01;
parameter D2LN_TX_REASGN_C = 2'b10;
parameter D2LN_RX_HS_21BIT_MODE = 1'b0;
parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1;
parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001;
parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100;
parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1;
parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001;
parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100;
parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1;
parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001;
parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100;
parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0;
parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001;
parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100;
parameter D2LN_RX_W_LENDIAN = 1'b1;
parameter D2LN_RX_REASGN_A = 2'b00;
parameter D2LN_RX_REASGN_B = 2'b01;
parameter D2LN_RX_REASGN_C = 2'b10;
parameter EQ_RS_LN2 = 3'b001;
parameter EQ_CS_LN2 = 3'b101;
parameter PGA_GAIN_LN2 = 4'b0110;
parameter PGA_BIAS_LN2 = 4'b1000;
parameter EQ_PBIAS_LN2 = 4'b0100;
parameter EQ_ZLD_LN2 = 4'b1000;
endmodule
module GTR12_QUAD (...);
endmodule
@ -1926,6 +2464,18 @@ endmodule
module GTR12_PMAC (...);
endmodule
module GTR12_QUADA (...);
endmodule
module GTR12_UPARA (...);
endmodule
module GTR12_PMACA (...);
endmodule
module GTR12_QUADB (...);
endmodule
module DQS (...);
input DQSIN,PCLK,FCLK,RESET;
input [3:0] READ;
@ -1941,4 +2491,3 @@ parameter RD_PNTR = 3'b000;
parameter DQS_MODE = "X1";
parameter HWL = "false";
endmodule

60
tests/opt/bug5164.ys Normal file
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@ -0,0 +1,60 @@
read_rtlil <<EOT
module \module137
wire input 1 \clk
wire width 1 output 1 \qa
wire width 1 \qb
cell $dff \dffa
parameter \CLK_POLARITY 1
parameter \WIDTH 1
connect \CLK \clk
connect \D \qb
connect \Q \qa
end
cell $dff \dffb
parameter \CLK_POLARITY 1
parameter \WIDTH 1
connect \CLK \clk
connect \D 1'x
connect \Q \qb
end
end
EOT
equiv_opt -assert opt_dff -sat
design -reset
read_rtlil <<EOT
module \module137
wire output 1 width 9 $2\reg204[8:0]
wire input 1 \clk
wire width 9 $auto$wreduce.cc:514:run$19340
wire width 9 $auto$wreduce.cc:514:run$19341
wire width 15 \dffout
attribute \init 9'000000000
wire width 9 \reg204
cell $dff $auto$ff.cc:266:slice$26225
parameter \CLK_POLARITY 1
parameter \WIDTH 15
connect \CLK \clk
connect \D { 9'x \reg204 [8:3] }
connect \Q \dffout
end
cell $dff $auto$ff.cc:266:slice$26292
parameter \CLK_POLARITY 1
parameter \WIDTH 9
connect \CLK \clk
connect \D $2\reg204[8:0]
connect \Q \reg204
end
cell $mux $procmux$4510
parameter \WIDTH 9
connect \A 9'x
connect \B 9'x
connect \S 1'x
connect \Y $auto$wreduce.cc:514:run$19340
end
connect $2\reg204[8:0] $auto$wreduce.cc:514:run$19340
connect $auto$wreduce.cc:514:run$19341 [8:3] 6'000000
end
EOT
equiv_opt -assert opt_dff -sat

57
tests/proc/case_attr.ys Normal file
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@ -0,0 +1,57 @@
read_verilog -sv << EOF
module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
always @* begin
W = F;
(* full_case *)
case (C)
A: W = D;
B: W = E;
endcase
end
always @* begin
X = F;
case (C)
A: X = D;
B: X = E;
endcase
end
always @* begin
Y = F;
(* full_case, parallel_case *)
case (C)
A: Y = D;
B: Y = E;
endcase
end
always @* begin
Z = F;
(* parallel_case *)
case (C)
A: Z = D;
B: Z = E;
endcase
end
endmodule
EOF
prep
# For the ones which use full_case, the F signal shouldn't be included in
# the input cone of W and Y.
select -set full o:W o:Y %u %ci*
select -assert-none i:F @full %i
select -assert-count 1 o:X %ci* i:F %i
select -assert-count 1 o:Z %ci* i:F %i
# And for parallel_case there should be 1 $pmux compared to the 2 $mux
# cells without.
select -assert-none o:W %ci* t:$pmux %i
select -assert-none o:X %ci* t:$pmux %i
select -assert-count 1 o:Y %ci* t:$pmux %i
select -assert-count 1 o:Z %ci* t:$pmux %i
select -assert-count 2 o:W %ci* t:$mux %i
select -assert-count 2 o:X %ci* t:$mux %i
select -assert-none o:Y %ci* t:$mux %i
select -assert-none o:Z %ci* t:$mux %i

32
tests/various/splitnets.ys Normal file
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@ -0,0 +1,32 @@
read_verilog <<EOT
module test_module (
a,
b,
x,
y
);
input [0:0] a;
output [0:0] b;
input [1:0] x;
output [1:0] y;
assign b = a;
assign y = x;
endmodule
EOT
proc
splitnets -ports -format __:
select -assert-count 0 w:a;
select -assert-count 1 w:a_0_;
select -assert-count 0 w:a_1_;
select -assert-count 0 w:b;
select -assert-count 1 w:b_0_;
select -assert-count 0 w:b_1_;
select -assert-count 0 w:x;
select -assert-count 1 w:x_0_;
select -assert-count 1 w:x_1_;
select -assert-count 0 w:y;
select -assert-count 1 w:y_0_;
select -assert-count 1 w:y_1_;

1
tests/verific/run-test.sh
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@ -2,3 +2,4 @@
set -eu
source ../gen-tests-makefile.sh
generate_mk --yosys-scripts --bash
sed -i '1i\export ASAN_OPTIONS=halt_on_error=0' run-test.mk

5
tests/verilog/bug5160.v Normal file
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@ -0,0 +1,5 @@
// Regression test for bug mentioned in #5160:
// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
module top;
initial $display( "\\" );
endmodule

54
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@ -0,0 +1,54 @@
read_verilog -sv << EOF
module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
always_comb begin
W = F;
priority case (C)
A: W = D;
B: W = E;
endcase
end
always_comb begin
X = F;
case (C)
A: X = D;
B: X = E;
endcase
end
always_comb begin
Y = F;
unique case (C)
A: Y = D;
B: Y = E;
endcase
end
always_comb begin
Z = F;
unique0 case (C)
A: Z = D;
B: Z = E;
endcase
end
endmodule
EOF
prep
# For the ones which use priority/unique, the F signal shouldn't be included in
# the input cone of W and Y.
select -set full o:W o:Y %u %ci*
select -assert-none i:F @full %i
select -assert-count 1 o:X %ci* i:F %i
select -assert-count 1 o:Z %ci* i:F %i
# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
# cells without.
select -assert-none o:W %ci* t:$pmux %i
select -assert-none o:X %ci* t:$pmux %i
select -assert-count 1 o:Y %ci* t:$pmux %i
select -assert-count 1 o:Z %ci* t:$pmux %i
select -assert-count 2 o:W %ci* t:$mux %i
select -assert-count 2 o:X %ci* t:$mux %i
select -assert-none o:Y %ci* t:$mux %i
select -assert-none o:Z %ci* t:$mux %i

54
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@ -0,0 +1,54 @@
read_verilog -sv << EOF
module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
always_comb begin
W = F;
priority if (C == A)
W = D;
else if (C == B)
W = E;
end
always_comb begin
X = F;
if (C == A)
X = D;
else if (C == B)
X = E;
end
always_comb begin
Y = F;
unique if (C == A)
Y = D;
else if (C == B)
Y = E;
end
always_comb begin
Z = F;
unique0 if (C == A)
Z = D;
else if (C == B)
Z = E;
end
endmodule
EOF
prep
# For the ones which use priority/unique, the F signal shouldn't be included in
# the input cone of W and Y.
select -set full o:W o:Y %u %ci*
select -assert-none i:F @full %i
select -assert-count 1 o:X %ci* i:F %i
select -assert-count 1 o:Z %ci* i:F %i
# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
# cells without.
select -assert-none o:W %ci* t:$pmux %i
select -assert-none o:X %ci* t:$pmux %i
select -assert-count 1 o:Y %ci* t:$pmux %i
select -assert-count 1 o:Z %ci* t:$pmux %i
select -assert-count 2 o:W %ci* t:$mux %i
select -assert-count 2 o:X %ci* t:$mux %i
select -assert-none o:Y %ci* t:$mux %i
select -assert-none o:Z %ci* t:$mux %i