diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 0c3146e41..d7ceb3fe3 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -36,7 +36,7 @@ jobs: vs-build: name: Visual Studio build - runs-on: windows-2019 + runs-on: windows-latest needs: [vs-prep, pre_job] if: needs.pre_job.outputs.should_skip != 'true' steps: diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index b88662f0f..22d3a94f8 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -40,6 +40,7 @@ jobs: strategy: matrix: os: [ubuntu-latest, macos-latest] + sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -57,7 +58,7 @@ jobs: mkdir build cd build make -f ../Makefile config-$CC - echo 'SANITIZER = undefined' >> Makefile.conf + echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf make -f ../Makefile -j$procs ENABLE_LTO=1 - name: Log yosys-config output @@ -73,7 +74,7 @@ jobs: - name: Store build artifact uses: actions/upload-artifact@v4 with: - name: build-${{ matrix.os }} + name: build-${{ matrix.os }}-${{ matrix.sanitizer }} path: build.tar retention-days: 1 @@ -84,10 +85,12 @@ jobs: if: needs.pre_job.outputs.should_skip != 'true' env: CC: clang + ASAN_OPTIONS: halt_on_error=1 UBSAN_OPTIONS: halt_on_error=1 strategy: matrix: os: [ubuntu-latest, macos-latest] + sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -136,7 +139,7 @@ jobs: - name: Download build artifact uses: actions/download-artifact@v4 with: - name: build-${{ matrix.os }} + name: build-${{ matrix.os }}-${{ matrix.sanitizer }} - name: Uncompress build shell: bash @@ -168,6 +171,7 @@ jobs: strategy: matrix: os: [ubuntu-latest] + sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -181,7 +185,7 @@ jobs: - name: Download build artifact uses: actions/download-artifact@v4 with: - name: build-${{ matrix.os }} + name: build-${{ matrix.os }}-${{ matrix.sanitizer }} - name: Uncompress build shell: bash diff --git a/CHANGELOG b/CHANGELOG index 537c5682d..d8f2f8804 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,9 +2,16 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.54 .. Yosys 0.55-dev +Yosys 0.55 .. Yosys 0.56-dev -------------------------- +Yosys 0.54 .. Yosys 0.55 +-------------------------- + * Various + - read_verilog: Implemented SystemVerilog unique/priority if. + - "attrmap" pass is able to alter memory attributes. + - verific: Support SVA followed-by operator in cover mode. + Yosys 0.53 .. Yosys 0.54 -------------------------- * New commands and options diff --git a/Makefile b/Makefile index b53526039..b7928f33a 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+0 +YOSYS_VER := 0.55+0 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -183,7 +183,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 60f126c.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/cell/word_mux.rst b/docs/source/cell/word_mux.rst index 3eca310f3..234d1016b 100644 --- a/docs/source/cell/word_mux.rst +++ b/docs/source/cell/word_mux.rst @@ -24,8 +24,8 @@ are zero, the value from ``A`` input is sent to the output. If the :math:`n`\ 'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of the ``B`` input is sent to the output. When more than one bit from ``S`` is set the output is undefined. Cells of this type are used to model "parallel cases" -(defined by using the ``parallel_case`` attribute or detected by an -optimization). +(defined by using the ``parallel_case`` attribute, the ``unique`` or ``unique0`` +SystemVerilog keywords, or detected by an optimization). The `$tribuf` cell is used to implement tristate logic. Cells of this type have a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A`` diff --git a/docs/source/conf.py b/docs/source/conf.py index 100605336..05dcb7d5f 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2025 YosysHQ GmbH' -yosys_ver = "0.54" +yosys_ver = "0.55" # select HTML theme html_theme = 'furo-ys' diff --git a/docs/source/yosys_internals/verilog.rst b/docs/source/yosys_internals/verilog.rst index eef215e5d..0039aaab7 100644 --- a/docs/source/yosys_internals/verilog.rst +++ b/docs/source/yosys_internals/verilog.rst @@ -377,7 +377,7 @@ from SystemVerilog: - Assignments within expressions are supported. - The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are - accepted on ``if`` and ``case`` conditionals. (Those keywords are currently - handled in the same way as their equivalent ``full_case`` and - ``parallel_case`` attributes on ``case`` statements, and checked - for syntactic validity but otherwise ignored on ``if`` statements.) + supported on ``if`` and ``case`` conditionals. (The Verilog frontend + will process conditionals using these keywords by annotating their + representation with the appropriate ``full_case`` and/or ``parallel_case`` + attributes, which are described above.) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d12f8a5a5..d83db3410 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3465,11 +3465,13 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); + RuntimeFlags::SetVar("veri_replace_const_exprs", 1); #endif #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); + RuntimeFlags::SetVar("vhdl_replace_const_exprs", 1); RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 860d3c166..7652f8130 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1613,7 +1613,10 @@ struct VerificSvaImporter } else if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION || - inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) + inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || + (mode_cover && ( + inst->Type() == PRIM_SVA_OVERLAPPED_FOLLOWED_BY || + inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION))) { Net *antecedent_net = inst->GetInput1(); Net *consequent_net = inst->GetInput2(); @@ -1621,7 +1624,7 @@ struct VerificSvaImporter SvaFsm antecedent_fsm(clocking, trig); node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net); - if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) { + if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || inst->Type() == PRIM_SVA_NON_OVERLAPPED_FOLLOWED_BY) { int next_node = antecedent_fsm.createNode(); antecedent_fsm.createEdge(node, next_node); node = next_node; diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 14a0f16c0..1f272ca4f 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -753,7 +753,7 @@ struct VerilogFileList : public Pass { break; } - extra_args(args, argidx, design); + extra_args(args, argidx, design, false); } } VerilogFilelist; diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8a3734302..40162b8d3 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s } \" { BEGIN(STRING); } -\\. { yymore(); real_location = old_location; } +([^\\"]|\\.)+ { yymore(); real_location = old_location; } \" { BEGIN(0); char *yystr = strdup(yytext); @@ -376,7 +376,6 @@ TIME_SCALE_SUFFIX [munpf]?s free(yystr); return TOK_STRING; } -. { yymore(); real_location = old_location; } and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { yylval->string = new std::string(yytext); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index fc236fa29..17edc357d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2873,16 +2873,37 @@ behavioral_stmt: ast_stack.pop_back(); } | if_attr TOK_IF '(' expr ')' { - AstNode *node = new AstNode(AST_CASE); + AstNode *node = 0; AstNode *block = new AstNode(AST_BLOCK); - AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block); + AstNode *context = ast_stack.back(); + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) { + AstNode *outer = ast_stack[ast_stack.size() - 2]; + log_assert (outer && outer->type == AST_CASE); + if (outer->get_bool_attribute(ID::parallel_case)) { + // parallel "else if": append condition to outer "if" + node = outer; + log_assert (node->children.size()); + ast_stack.pop_back(); + delete node->children.back(); + node->children.pop_back(); + ast_stack.push_back(block); + } else if (outer->get_bool_attribute(ID::full_case)) + (*$1)[ID::full_case] = AstNode::mkconst_int(1, false); + } + AstNode *expr = new AstNode(AST_REDUCE_BOOL, $4); + if (!node) { + // not parallel "else if": begin new construction + node = new AstNode(AST_CASE); + append_attr(node, $1); + ast_stack.back()->children.push_back(node); + node->children.push_back(node->get_bool_attribute(ID::parallel_case) ? AstNode::mkconst_int(1, false, 1) : expr); + } else + free_attr($1); + AstNode *cond = new AstNode(AST_COND, node->get_bool_attribute(ID::parallel_case) ? expr : AstNode::mkconst_int(1, false, 1), block); SET_AST_NODE_LOC(cond, @4, @4); - ast_stack.back()->children.push_back(node); - node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4)); node->children.push_back(cond); ast_stack.push_back(node); ast_stack.push_back(block); - append_attr(node, $1); } behavioral_stmt { SET_AST_NODE_LOC(ast_stack.back(), @7, @7); } optional_else { @@ -2908,21 +2929,25 @@ if_attr: } | attr TOK_UNIQUE0 { AstNode *context = ast_stack.back(); - if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) ) + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) frontend_verilog_yyerror("unique0 keyword cannot be used for 'else if' branch."); - $$ = $1; // accept unique0 keyword, but ignore it for now + (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false); + $$ = $1; } | attr TOK_PRIORITY { AstNode *context = ast_stack.back(); - if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) ) + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) frontend_verilog_yyerror("priority keyword cannot be used for 'else if' branch."); - $$ = $1; // accept priority keyword, but ignore it for now + (*$1)[ID::full_case] = AstNode::mkconst_int(1, false); + $$ = $1; } | attr TOK_UNIQUE { AstNode *context = ast_stack.back(); - if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) ) + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) frontend_verilog_yyerror("unique keyword cannot be used for 'else if' branch."); - $$ = $1; // accept unique keyword, but ignore it for now + (*$1)[ID::full_case] = AstNode::mkconst_int(1, false); + (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false); + $$ = $1; }; case_attr: diff --git a/kernel/driver.cc b/kernel/driver.cc index 9acc58dc4..76c11853e 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -20,6 +20,7 @@ #include "kernel/yosys.h" #include "kernel/hashlib.h" #include "libs/sha1/sha1.h" +#define CXXOPTS_VECTOR_DELIMITER '\0' #include "libs/cxxopts/include/cxxopts.hpp" #include diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7d0d688fc..196b78186 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -187,12 +187,14 @@ int run_command(const std::string &command, std::functionwires()) { - if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire)) + if (((wire->width > 1) || (wire->has_attribute(ID::single_bit_vector))) + && (wire->port_id == 0 || flag_ports) + && design->selected(module, wire)) { + wire->attributes.erase(ID::single_bit_vector); worker.splitmap[wire] = std::vector(); + } } for (auto &it : worker.splitmap) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 8539432c0..4ed4b0cb6 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -738,7 +738,11 @@ struct OptDffWorker ModWalker modwalker(module->design, module); QuickConeSat qcsat(modwalker); - // Run as a separate sub-pass, so that we don't mutate (non-FF) cells under ModWalker. + // Defer mutating cells by removing them/emiting new flip flops so that + // cell references in modwalker are not invalidated + std::vector cells_to_remove; + std::vector ffs_to_emit; + bool did_something = false; for (auto cell : module->selected_cells()) { if (!RTLIL::builtin_ff_cell_types().count(cell->type)) @@ -830,16 +834,20 @@ struct OptDffWorker if (!removed_sigbits.count(i)) keep_bits.push_back(i); if (keep_bits.empty()) { - module->remove(cell); + cells_to_remove.emplace_back(cell); did_something = true; continue; } ff = ff.slice(keep_bits); ff.cell = cell; - ff.emit(); + ffs_to_emit.emplace_back(ff); did_something = true; } } + for (auto* cell : cells_to_remove) + module->remove(cell); + for (auto& ff : ffs_to_emit) + ff.emit(); return did_something; } }; diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 96e65ff2e..7f5bfc94f 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -263,33 +263,27 @@ struct AttrmapPass : public Pass { if (modattr_mode) { - for (auto module : design->selected_whole_modules()) + for (auto module : design->all_selected_whole_modules()) attrmap_apply(stringf("%s", log_id(module)), actions, module->attributes); } else { - for (auto module : design->selected_modules()) + for (auto module : design->all_selected_modules()) { - for (auto wire : module->selected_wires()) - attrmap_apply(stringf("%s.%s", log_id(module), log_id(wire)), actions, wire->attributes); + for (auto memb : module->selected_members()) + attrmap_apply(stringf("%s.%s", log_id(module), log_id(memb)), actions, memb->attributes); - for (auto cell : module->selected_cells()) - attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes); - - for (auto proc : module->processes) + // attrmap already applied to process itself during above loop, but not its children + for (auto proc : module->selected_processes()) { - if (!design->selected(module, proc.second)) - continue; - attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes); - - std::vector all_cases = {&proc.second->root_case}; + std::vector all_cases = {&proc->root_case}; while (!all_cases.empty()) { RTLIL::CaseRule *cs = all_cases.back(); all_cases.pop_back(); - attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes); + attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc)), actions, cs->attributes); for (auto &sw : cs->switches) { - attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes); + attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc)), actions, sw->attributes); all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end()); } } diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py index be2e0eff3..7a7c9ac0a 100644 --- a/techlibs/gowin/cells_xtra.py +++ b/techlibs/gowin/cells_xtra.py @@ -11,6 +11,7 @@ import re class State(Enum): OUTSIDE = auto() IN_MODULE = auto() + IN_MODULE_MULTILINE = auto() IN_PARAMETER = auto() _skip = { # These are already described, no need to extract them from the vendor files @@ -47,12 +48,20 @@ def xtract_cells_decl(dir, fout): fout.write(l) if l[-1] != '\n': fout.write('\n') + if l.rstrip()[-1] != ';': + state = State.IN_MODULE_MULTILINE elif l.startswith('parameter') and state == State.IN_MODULE: fout.write(l) if l.rstrip()[-1] == ',': state = State.IN_PARAMETER if l[-1] != '\n': fout.write('\n') + elif l and state == State.IN_MODULE_MULTILINE: + fout.write(l) + if l[-1] != '\n': + fout.write('\n') + if l.rstrip()[-1] == ';': + state = State.IN_MODULE elif state == State.IN_PARAMETER: fout.write(l) if l.rstrip()[-1] == ';': @@ -65,6 +74,7 @@ def xtract_cells_decl(dir, fout): if l[-1] != '\n': fout.write('\n') + if __name__ == '__main__': parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.') parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/') diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v index d19435f85..c82f6af25 100644 --- a/techlibs/gowin/cells_xtra_gw5a.v +++ b/techlibs/gowin/cells_xtra_gw5a.v @@ -80,19 +80,8 @@ endmodule module MIPI_OBUF_A (...); output O, OB; input I, IB, IL, MODESEL; -endmodule - -module IBUF_R (...); -input I; -input RTEN; -output O; -endmodule - -module IOBUF_R (...); -input I,OEN; -input RTEN; -output O; -inout IO; +inout IO, IOB; +input OEN, OENB; endmodule module ELVDS_IOBUF_R (...); @@ -113,6 +102,21 @@ input I, IB; input ADCEN; endmodule +module MIPI_CPHY_IBUF (...); +output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2; +inout IO0, IOB0, IO1, IOB1, IO2, IOB2; +input I0, IB0, I1, IB1, I2, IB2; +input OEN, OENB; +input HSEN; +endmodule + +module MIPI_CPHY_OBUF (...); +output O0, OB0, O1, OB1, O2, OB2; +input I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2; +inout IO0, IOB0, IO1, IOB1, IO2, IOB2; +input OEN, OENB, MODESEL, VCOME; +endmodule + module SDPB (...); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; @@ -598,8 +602,8 @@ endmodule module SDP36KE (...); -parameter ECC_WRITE_EN="FALSE"; -parameter ECC_READ_EN="FALSE"; +parameter ECC_WRITE_EN="TRUE"; +parameter ECC_READ_EN="TRUE"; parameter READ_MODE = 1'b0; parameter BLK_SEL_A = 3'b000; parameter BLK_SEL_B = 3'b000; @@ -764,6 +768,14 @@ output [7:0] ECCP; endmodule +module SDP136K (...); +input CLKA, CLKB; +input WE, RE; +input [10:0] ADA, ADB; +input [67:0] DI; +output [67:0] DO; +endmodule + module MULTADDALU12X12 (...); parameter A0REG_CLK = "BYPASS"; parameter A0REG_CE = "CE0"; @@ -980,6 +992,24 @@ input PSEL; input PADDSUB; endmodule +module MULTACC (...); +output [23:0] DATAO, CASO; +input CE, CLK; +input [5:0] COFFIN0, COFFIN1, COFFIN2; +input [9:0] DATAIN0, DATAIN1; +input [9:0] DATAIN2; +input RSTN; +input [23:0] CASI; +parameter COFFIN_WIDTH = 4; +parameter DATAIN_WIDTH = 8; +parameter IREG = 1'b0; +parameter OREG = 1'b0; +parameter PREG = 1'b0; +parameter ACC_EN = "FALSE"; +parameter CASI_EN = "FALSE"; +parameter CASO_EN = "FALSE"; +endmodule + module IDDR_MEM (...); input D, ICLK, PCLK; input [2:0] WADDR; @@ -1048,6 +1078,12 @@ output Q0, Q1; endmodule +module OSER14 (...); +input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13; +input PCLK, FCLK, RESET; +output Q; +endmodule + module IODELAY (...); parameter C_STATIC_DLY = 0; parameter DYN_DLY_EN = "FALSE"; @@ -1066,13 +1102,39 @@ output [31:0] Q; input D; input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; input RESET; -output DF; -input SDTAP; -input VALUE; -input [7:0] DLYSTEP; -parameter C_STATIC_DLY = 0; -parameter DYN_DLY_EN = "FALSE"; -parameter ADAPT_EN = "FALSE"; +output DF0, DF1; +input SDTAP0, SDTAP1; +input VALUE0,VALUE1; +input [7:0] DLYSTEP0,DLYSTEP1; +parameter C_STATIC_DLY_0 = 0; +parameter DYN_DLY_EN_0 = "FALSE"; +parameter ADAPT_EN_0 = "FALSE"; +parameter C_STATIC_DLY_1 = 0; +parameter DYN_DLY_EN_1 = "FALSE"; +parameter ADAPT_EN_1 = "FALSE"; +endmodule + +module OSIDES64 (...); +output [63:0] Q; +input D; +input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; +input RESET; +output DF0, DF1, DF2, DF3; +input SDTAP0, SDTAP1, SDTAP2, SDTAP3; +input VALUE0, VALUE1, VALUE2, VALUE3; +input [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3; +parameter C_STATIC_DLY_0 = 0; +parameter DYN_DLY_EN_0 = "FALSE"; +parameter ADAPT_EN_0 = "FALSE"; +parameter C_STATIC_DLY_1 = 0; +parameter DYN_DLY_EN_1 = "FALSE"; +parameter ADAPT_EN_1 = "FALSE"; +parameter C_STATIC_DLY_2 = 0; +parameter DYN_DLY_EN_2 = "FALSE"; +parameter ADAPT_EN_2 = "FALSE"; +parameter C_STATIC_DLY_3 = 0; +parameter DYN_DLY_EN_3 = "FALSE"; +parameter ADAPT_EN_3 = "FALSE"; endmodule module DCE (...); @@ -1132,6 +1194,17 @@ output OSCOUT; input OSCEN; endmodule +module OSCB (...); +parameter FREQ_MODE = "25"; +parameter FREQ_DIV = 10; +parameter DYN_TRIM_EN = "FALSE"; +output OSCOUT; +output OSCREF; +input OSCEN, FMODE; +input [7:0] RTRIM; +input [5:0] RTCTRIM; +endmodule + module PLL (...); input CLKIN; input CLKFB; @@ -1571,8 +1644,8 @@ input ADWSEL; endmodule module OTP (...); -parameter MODE = 1'b0; -input READ, SHIFT; +parameter MODE = 2'b01; +input CLK, READ, SHIFT; output DOUT; endmodule @@ -1615,6 +1688,31 @@ input ERR0INJECT,ERR1INJECT; input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule +module CMSERB (...); +output RUNNING; +output CRCERR; +output CRCDONE; +output ECCCORR; +output ECCUNCORR; +output [12:0] ERRLOC; +output ECCDEC; +output DSRRD; +output DSRWR; +output ASRRESET; +output ASRINC; +output REFCLK; +input CLK; +input [2:0] SEREN; +input ERR0INJECT,ERR1INJECT; +input [6:0] ERRINJ0LOC,ERRINJ1LOC; +endmodule + +module SAMBA (...); +parameter MODE = 2'b00; +input SPIAD; +input LOAD; +endmodule + module ADCLRC (...); endmodule @@ -1624,6 +1722,12 @@ endmodule module ADC (...); endmodule +module ADC_SAR (...); +endmodule + +module LICD (...); +endmodule + module MIPI_DPHY (...); output RX_CLK_O, TX_CLK_O; output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; @@ -1632,6 +1736,7 @@ input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN; output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P; inout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P; input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, + LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK; input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X; input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN; input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; @@ -1639,6 +1744,8 @@ input HSTXD_VLD; input CK0, CK90, CK180, CK270; input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, + HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; output [7:0] MRDATA; input MA_INC, MCLK; @@ -1714,7 +1821,7 @@ parameter RX_RD_START_DEPTH = 5'b00001; parameter RX_SYNC_MODE = 1'b0 ; parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; -parameter RX_WORD_LITTLE_ENDIAN = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; parameter TX_BYPASS_MODE = 1'b0 ; parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; parameter TX_OCLK_USE_CIBCLK = 1'b0 ; @@ -1917,6 +2024,437 @@ parameter TEST_P_IMP_LN3 = 1'b0 ; parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule +module MIPI_DPHYA (...); +output RX_CLK_O, TX_CLK_O; +output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; +output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; +input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN; +output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P; +inout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P; +input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, + LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK; +input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X; +input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN; +input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; +input HSTXD_VLD; +input CK0, CK90, CK180, CK270; +input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; +input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, + HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; +input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; +output [7:0] MRDATA; +input MA_INC, MCLK; +input [1:0] MOPCODE; +input [7:0] MWDATA; +input SPLL_CKN, SPLL_CKP; +output ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK; +output D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE; +output D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR; +input D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ; +input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK; +input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK; +input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK; +input ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK; +parameter TX_PLLCLK = "NONE"; +parameter RX_ALIGN_BYTE = 8'b10111000 ; +parameter RX_HS_8BIT_MODE = 1'b0 ; +parameter RX_LANE_ALIGN_EN = 1'b0 ; +parameter TX_HS_8BIT_MODE = 1'b0 ; +parameter HSREG_EN_LN0 = 1'b0; +parameter HSREG_EN_LN1 = 1'b0; +parameter HSREG_EN_LN2 = 1'b0; +parameter HSREG_EN_LN3 = 1'b0; +parameter HSREG_EN_LNCK = 1'b0; +parameter LANE_DIV_SEL = 2'b00; +parameter HSRX_EN = 1'b1 ; +parameter HSRX_LANESEL = 4'b1111 ; +parameter HSRX_LANESEL_CK = 1'b1 ; +parameter HSTX_EN_LN0 = 1'b0 ; +parameter HSTX_EN_LN1 = 1'b0 ; +parameter HSTX_EN_LN2 = 1'b0 ; +parameter HSTX_EN_LN3 = 1'b0 ; +parameter HSTX_EN_LNCK = 1'b0 ; +parameter LPTX_EN_LN0 = 1'b1 ; +parameter LPTX_EN_LN1 = 1'b1 ; +parameter LPTX_EN_LN2 = 1'b1 ; +parameter LPTX_EN_LN3 = 1'b1 ; +parameter LPTX_EN_LNCK = 1'b1 ; +parameter TXDP_EN_LN0 = 1'b0 ; +parameter TXDP_EN_LN1 = 1'b0 ; +parameter TXDP_EN_LN2 = 1'b0 ; +parameter TXDP_EN_LN3 = 1'b0 ; +parameter TXDP_EN_LNCK = 1'b0 ; +parameter SPLL_DIV_SEL = 2'b00; +parameter DPHY_CK_SEL = 2'b01; +parameter CKLN_DELAY_EN = 1'b0; +parameter CKLN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DELAY_EN = 1'b0; +parameter D0LN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DESKEW_BYPASS = 1'b0; +parameter D1LN_DELAY_EN = 1'b0; +parameter D1LN_DELAY_OVR_VAL = 7'b0000000; +parameter D1LN_DESKEW_BYPASS = 1'b0; +parameter D2LN_DELAY_EN = 1'b0; +parameter D2LN_DELAY_OVR_VAL = 7'b0000000; +parameter D2LN_DESKEW_BYPASS = 1'b0; +parameter D3LN_DELAY_EN = 1'b0; +parameter D3LN_DELAY_OVR_VAL = 7'b0000000; +parameter D3LN_DESKEW_BYPASS = 1'b0; +parameter DESKEW_EN_LOW_DELAY = 1'b0; +parameter DESKEW_EN_ONE_EDGE = 1'b0; +parameter DESKEW_FAST_LOOP_TIME = 4'b0000; +parameter DESKEW_FAST_MODE = 1'b0; +parameter DESKEW_HALF_OPENING = 6'b010110; +parameter DESKEW_LSB_MODE = 2'b00; +parameter DESKEW_M = 3'b011; +parameter DESKEW_M_TH = 13'b0000110100110; +parameter DESKEW_MAX_SETTING = 7'b0100001; +parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; +parameter DESKEW_RST_BYPASS = 1'b0 ; +parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; +parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; +parameter RX_INVERT = 1'b0 ; +parameter RX_ONE_BYTE0_MATCH = 1'b0 ; +parameter RX_RD_START_DEPTH = 5'b00001; +parameter RX_SYNC_MODE = 1'b0 ; +parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; +parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter TX_BYPASS_MODE = 1'b0 ; +parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; +parameter TX_OCLK_USE_CIBCLK = 1'b0 ; +parameter TX_RD_START_DEPTH = 5'b00001; +parameter TX_SYNC_MODE = 1'b0 ; +parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter EQ_CS_LANE0 = 3'b100; +parameter EQ_CS_LANE1 = 3'b100; +parameter EQ_CS_LANE2 = 3'b100; +parameter EQ_CS_LANE3 = 3'b100; +parameter EQ_CS_LANECK = 3'b100; +parameter EQ_RS_LANE0 = 3'b100; +parameter EQ_RS_LANE1 = 3'b100; +parameter EQ_RS_LANE2 = 3'b100; +parameter EQ_RS_LANE3 = 3'b100; +parameter EQ_RS_LANECK = 3'b100; +parameter HSCLK_LANE_LN0 = 1'b0; +parameter HSCLK_LANE_LN1 = 1'b0; +parameter HSCLK_LANE_LN2 = 1'b0; +parameter HSCLK_LANE_LN3 = 1'b0; +parameter HSCLK_LANE_LNCK = 1'b1; +parameter ALP_ED_EN_LANE0 = 1'b1 ; +parameter ALP_ED_EN_LANE1 = 1'b1 ; +parameter ALP_ED_EN_LANE2 = 1'b1 ; +parameter ALP_ED_EN_LANE3 = 1'b1 ; +parameter ALP_ED_EN_LANECK = 1'b1 ; +parameter ALP_ED_TST_LANE0 = 1'b0 ; +parameter ALP_ED_TST_LANE1 = 1'b0 ; +parameter ALP_ED_TST_LANE2 = 1'b0 ; +parameter ALP_ED_TST_LANE3 = 1'b0 ; +parameter ALP_ED_TST_LANECK = 1'b0 ; +parameter ALP_EN_LN0 = 1'b0 ; +parameter ALP_EN_LN1 = 1'b0 ; +parameter ALP_EN_LN2 = 1'b0 ; +parameter ALP_EN_LN3 = 1'b0 ; +parameter ALP_EN_LNCK = 1'b0 ; +parameter ALP_HYS_EN_LANE0 = 1'b1 ; +parameter ALP_HYS_EN_LANE1 = 1'b1 ; +parameter ALP_HYS_EN_LANE2 = 1'b1 ; +parameter ALP_HYS_EN_LANE3 = 1'b1 ; +parameter ALP_HYS_EN_LANECK = 1'b1 ; +parameter ALP_TH_LANE0 = 4'b1000 ; +parameter ALP_TH_LANE1 = 4'b1000 ; +parameter ALP_TH_LANE2 = 4'b1000 ; +parameter ALP_TH_LANE3 = 4'b1000 ; +parameter ALP_TH_LANECK = 4'b1000 ; +parameter ANA_BYTECLK_PH = 2'b00 ; +parameter BIT_REVERSE_LN0 = 1'b0 ; +parameter BIT_REVERSE_LN1 = 1'b0 ; +parameter BIT_REVERSE_LN2 = 1'b0 ; +parameter BIT_REVERSE_LN3 = 1'b0 ; +parameter BIT_REVERSE_LNCK = 1'b0 ; +parameter BYPASS_TXHCLKEN = 1'b1 ; +parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; +parameter BYTE_CLK_POLAR = 1'b0 ; +parameter BYTE_REVERSE_LN0 = 1'b0 ; +parameter BYTE_REVERSE_LN1 = 1'b0 ; +parameter BYTE_REVERSE_LN2 = 1'b0 ; +parameter BYTE_REVERSE_LN3 = 1'b0 ; +parameter BYTE_REVERSE_LNCK = 1'b0 ; +parameter EN_CLKB1X = 1'b1 ; +parameter EQ_PBIAS_LANE0 = 4'b1000 ; +parameter EQ_PBIAS_LANE1 = 4'b1000 ; +parameter EQ_PBIAS_LANE2 = 4'b1000 ; +parameter EQ_PBIAS_LANE3 = 4'b1000 ; +parameter EQ_PBIAS_LANECK = 4'b1000 ; +parameter EQ_ZLD_LANE0 = 4'b1000 ; +parameter EQ_ZLD_LANE1 = 4'b1000 ; +parameter EQ_ZLD_LANE2 = 4'b1000 ; +parameter EQ_ZLD_LANE3 = 4'b1000 ; +parameter EQ_ZLD_LANECK = 4'b1000 ; +parameter HIGH_BW_LANE0 = 1'b1 ; +parameter HIGH_BW_LANE1 = 1'b1 ; +parameter HIGH_BW_LANE2 = 1'b1 ; +parameter HIGH_BW_LANE3 = 1'b1 ; +parameter HIGH_BW_LANECK = 1'b1 ; +parameter HSREG_VREF_CTL = 3'b100 ; +parameter HSREG_VREF_EN = 1'b1 ; +parameter HSRX_DLY_CTL_CK = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; +parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; +parameter HSRX_DLY_SEL_LANECK = 1'b0 ; +parameter HSRX_DUTY_LANE0 = 4'b1000 ; +parameter HSRX_DUTY_LANE1 = 4'b1000 ; +parameter HSRX_DUTY_LANE2 = 4'b1000 ; +parameter HSRX_DUTY_LANE3 = 4'b1000 ; +parameter HSRX_DUTY_LANECK = 4'b1000 ; +parameter HSRX_EQ_EN_LANE0 = 1'b1 ; +parameter HSRX_EQ_EN_LANE1 = 1'b1 ; +parameter HSRX_EQ_EN_LANE2 = 1'b1 ; +parameter HSRX_EQ_EN_LANE3 = 1'b1 ; +parameter HSRX_EQ_EN_LANECK = 1'b1 ; +parameter HSRX_IBIAS = 4'b0011 ; +parameter HSRX_IBIAS_TEST_EN = 1'b0 ; +parameter HSRX_IMARG_EN = 1'b0 ; +parameter HSRX_ODT_EN = 1'b1 ; +parameter HSRX_ODT_TST = 4'b0000 ; +parameter HSRX_ODT_TST_CK = 1'b0 ; +parameter HSRX_SEL = 4'b0000 ; +parameter HSRX_STOP_EN = 1'b0 ; +parameter HSRX_TST = 4'b0000 ; +parameter HSRX_TST_CK = 1'b0 ; +parameter HSRX_WAIT4EDGE = 1'b1 ; +parameter HYST_NCTL = 2'b01 ; +parameter HYST_PCTL = 2'b01 ; +parameter IBIAS_TEST_EN = 1'b0 ; +parameter LB_CH_SEL = 1'b0 ; +parameter LB_EN_LN0 = 1'b0 ; +parameter LB_EN_LN1 = 1'b0 ; +parameter LB_EN_LN2 = 1'b0 ; +parameter LB_EN_LN3 = 1'b0 ; +parameter LB_EN_LNCK = 1'b0 ; +parameter LB_POLAR_LN0 = 1'b0 ; +parameter LB_POLAR_LN1 = 1'b0 ; +parameter LB_POLAR_LN2 = 1'b0 ; +parameter LB_POLAR_LN3 = 1'b0 ; +parameter LB_POLAR_LNCK = 1'b0 ; +parameter LOW_LPRX_VTH = 1'b0 ; +parameter LPBK_DATA2TO1 = 4'b0000; +parameter LPBK_DATA2TO1_CK = 1'b0 ; +parameter LPBK_EN = 1'b0 ; +parameter LPBK_SEL = 4'b0000; +parameter LPBKTST_EN = 4'b0000; +parameter LPBKTST_EN_CK = 1'b0 ; +parameter LPRX_EN = 1'b1 ; +parameter LPRX_TST = 4'b0000; +parameter LPRX_TST_CK = 1'b0 ; +parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; +parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; +parameter LPTX_NIMP_LN0 = 3'b100 ; +parameter LPTX_NIMP_LN1 = 3'b100 ; +parameter LPTX_NIMP_LN2 = 3'b100 ; +parameter LPTX_NIMP_LN3 = 3'b100 ; +parameter LPTX_NIMP_LNCK = 3'b100 ; +parameter LPTX_PIMP_LN0 = 3'b100 ; +parameter LPTX_PIMP_LN1 = 3'b100 ; +parameter LPTX_PIMP_LN2 = 3'b100 ; +parameter LPTX_PIMP_LN3 = 3'b100 ; +parameter LPTX_PIMP_LNCK = 3'b100 ; +parameter MIPI_PMA_DIS_N = 1'b1 ; +parameter PGA_BIAS_LANE0 = 4'b1000 ; +parameter PGA_BIAS_LANE1 = 4'b1000 ; +parameter PGA_BIAS_LANE2 = 4'b1000 ; +parameter PGA_BIAS_LANE3 = 4'b1000 ; +parameter PGA_BIAS_LANECK = 4'b1000 ; +parameter PGA_GAIN_LANE0 = 4'b1000 ; +parameter PGA_GAIN_LANE1 = 4'b1000 ; +parameter PGA_GAIN_LANE2 = 4'b1000 ; +parameter PGA_GAIN_LANE3 = 4'b1000 ; +parameter PGA_GAIN_LANECK = 4'b1000 ; +parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; +parameter RX_ODT_TRIM_LANECK = 4'b1000 ; +parameter SLEWN_CTL_LN0 = 4'b1111 ; +parameter SLEWN_CTL_LN1 = 4'b1111 ; +parameter SLEWN_CTL_LN2 = 4'b1111 ; +parameter SLEWN_CTL_LN3 = 4'b1111 ; +parameter SLEWN_CTL_LNCK = 4'b1111 ; +parameter SLEWP_CTL_LN0 = 4'b1111 ; +parameter SLEWP_CTL_LN1 = 4'b1111 ; +parameter SLEWP_CTL_LN2 = 4'b1111 ; +parameter SLEWP_CTL_LN3 = 4'b1111 ; +parameter SLEWP_CTL_LNCK = 4'b1111 ; +parameter STP_UNIT = 2'b01 ; +parameter TERMN_CTL_LN0 = 4'b1000 ; +parameter TERMN_CTL_LN1 = 4'b1000 ; +parameter TERMN_CTL_LN2 = 4'b1000 ; +parameter TERMN_CTL_LN3 = 4'b1000 ; +parameter TERMN_CTL_LNCK = 4'b1000 ; +parameter TERMP_CTL_LN0 = 4'b1000 ; +parameter TERMP_CTL_LN1 = 4'b1000 ; +parameter TERMP_CTL_LN2 = 4'b1000 ; +parameter TERMP_CTL_LN3 = 4'b1000 ; +parameter TERMP_CTL_LNCK = 4'b1000 ; +parameter TEST_EN_LN0 = 1'b0 ; +parameter TEST_EN_LN1 = 1'b0 ; +parameter TEST_EN_LN2 = 1'b0 ; +parameter TEST_EN_LN3 = 1'b0 ; +parameter TEST_EN_LNCK = 1'b0 ; +parameter TEST_N_IMP_LN0 = 1'b0 ; +parameter TEST_N_IMP_LN1 = 1'b0 ; +parameter TEST_N_IMP_LN2 = 1'b0 ; +parameter TEST_N_IMP_LN3 = 1'b0 ; +parameter TEST_N_IMP_LNCK = 1'b0 ; +parameter TEST_P_IMP_LN0 = 1'b0 ; +parameter TEST_P_IMP_LN1 = 1'b0 ; +parameter TEST_P_IMP_LN2 = 1'b0 ; +parameter TEST_P_IMP_LN3 = 1'b0 ; +parameter TEST_P_IMP_LNCK = 1'b0 ; +endmodule + +module MIPI_CPHY (...); +output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD; +output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD; +output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD; +output D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR; +output [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA; +output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O; +output HSTX_FIFO_AE, HSTX_FIFO_AF; +output HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR; +output RX_CLK_MUXED; +output TX_CLK_1X_O; +output DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C; +output [7:0] MDRP_RDATA; +inout D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C; +input D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN; +input [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA; +input D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD; +input [1:0] D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS; +input D0LN_RX_CLK_1X_I,D1LN_RX_CLK_1X_I, D2LN_RX_CLK_1X_I; +input D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N; +input HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2; +input [7:0] MDRP_A_D_I; +input MDRP_A_INC_I; +input MDRP_CLK_I; +input [1:0] MDRP_OPCODE_I; +input PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX; +input ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; +input ARSTN_TX; +input RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; +input TX_CLK_1X_I; +input TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; +input TXHCLK_EN; +input DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2; +input GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270; +input HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; +input HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2; +input LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; +input SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP; +parameter TX_PLLCLK = "NONE"; +parameter D0LN_HS_TX_EN = 1'b1; +parameter D1LN_HS_TX_EN = 1'b1; +parameter D2LN_HS_TX_EN = 1'b1; +parameter D0LN_HS_RX_EN = 1'b1; +parameter D1LN_HS_RX_EN = 1'b1; +parameter D2LN_HS_RX_EN = 1'b1; +parameter TX_HS_21BIT_MODE = 1'b0; +parameter RX_OUTCLK_SEL = 2'b00; +parameter TX_W_LENDIAN = 1'b1; +parameter CLK_SEL = 2'b00; +parameter LNDIV_RATIO = 4'b0000; +parameter LNDIV_EN = 1'b0; +parameter D0LN_TX_REASGN_A = 2'b00; +parameter D0LN_TX_REASGN_B = 2'b01; +parameter D0LN_TX_REASGN_C = 2'b10; +parameter D0LN_RX_HS_21BIT_MODE = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D0LN_RX_W_LENDIAN = 1'b1; +parameter D0LN_RX_REASGN_A = 2'b00; +parameter D0LN_RX_REASGN_B = 2'b01; +parameter D0LN_RX_REASGN_C = 2'b10; +parameter HSRX_LNSEL = 3'b111; +parameter EQ_RS_LN0 = 3'b001; +parameter EQ_CS_LN0 = 3'b101; +parameter PGA_GAIN_LN0 = 4'b0110; +parameter PGA_BIAS_LN0 = 4'b1000; +parameter EQ_PBIAS_LN0 = 4'b0100; +parameter EQ_ZLD_LN0 = 4'b1000; +parameter D1LN_TX_REASGN_A = 2'b00; +parameter D1LN_TX_REASGN_B = 2'b01; +parameter D1LN_TX_REASGN_C = 2'b10; +parameter D1LN_RX_HS_21BIT_MODE = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D1LN_RX_W_LENDIAN = 1'b1; +parameter D1LN_RX_REASGN_A = 2'b00; +parameter D1LN_RX_REASGN_B = 2'b01; +parameter D1LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN1 = 3'b001; +parameter EQ_CS_LN1 = 3'b101; +parameter PGA_GAIN_LN1 = 4'b0110; +parameter PGA_BIAS_LN1 = 4'b1000; +parameter EQ_PBIAS_LN1 = 4'b0100; +parameter EQ_ZLD_LN1 = 4'b1000; +parameter D2LN_TX_REASGN_A = 2'b00; +parameter D2LN_TX_REASGN_B = 2'b01; +parameter D2LN_TX_REASGN_C = 2'b10; +parameter D2LN_RX_HS_21BIT_MODE = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D2LN_RX_W_LENDIAN = 1'b1; +parameter D2LN_RX_REASGN_A = 2'b00; +parameter D2LN_RX_REASGN_B = 2'b01; +parameter D2LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN2 = 3'b001; +parameter EQ_CS_LN2 = 3'b101; +parameter PGA_GAIN_LN2 = 4'b0110; +parameter PGA_BIAS_LN2 = 4'b1000; +parameter EQ_PBIAS_LN2 = 4'b0100; +parameter EQ_ZLD_LN2 = 4'b1000; +endmodule + module GTR12_QUAD (...); endmodule @@ -1926,6 +2464,18 @@ endmodule module GTR12_PMAC (...); endmodule +module GTR12_QUADA (...); +endmodule + +module GTR12_UPARA (...); +endmodule + +module GTR12_PMACA (...); +endmodule + +module GTR12_QUADB (...); +endmodule + module DQS (...); input DQSIN,PCLK,FCLK,RESET; input [3:0] READ; @@ -1941,4 +2491,3 @@ parameter RD_PNTR = 3'b000; parameter DQS_MODE = "X1"; parameter HWL = "false"; endmodule - diff --git a/tests/opt/bug5164.ys b/tests/opt/bug5164.ys new file mode 100644 index 000000000..4ee71fe45 --- /dev/null +++ b/tests/opt/bug5164.ys @@ -0,0 +1,60 @@ +read_rtlil <