From 547382504b0d2b842b2d326079f621c164c7c194 Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 8 May 2025 10:37:04 +1200 Subject: [PATCH 01/30] Update verilog_frontend.cc `read_verilog_file_list` should not try to read arguments as selection args. Without this, trying to pass a file without a `-f|-F` flag is misleading, in the best case giving a warning about the selection not matching any module, or in worst case just doing nothing (if the filename is a valid selection). --- frontends/verilog/verilog_frontend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 14a0f16c0..1f272ca4f 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -753,7 +753,7 @@ struct VerilogFileList : public Pass { break; } - extra_args(args, argidx, design); + extra_args(args, argidx, design, false); } } VerilogFilelist; From 370d5871f4bd04d6ccd57457827dc1dfcaf74d1e Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Thu, 29 May 2025 20:42:49 -0600 Subject: [PATCH 02/30] verilog: implement SystemVerilog unique/unique0/priority if semantics. There are two elements involved: 1) Apply the relevant full_case and/or parallel_case attribute(s) to the generated AST_CASE node(s), so that the existing AST frontend and subsequent passes will generate RTLIL with appropriate behaviour. (This is handled in the parser "if_attr" non-terminal.) 2) Rearrange the AST_CASE structure when necessary. For "priority if" (i.e., full_case), this requires only ensuring that directly nested "else if" branches also inherit the full_case attribute. For "unique if" and "unique0 if" (i.e., parallel_case+full_case and parallel_case alone), there are two steps: a) Flatten the AST_CASE structure such that any direct "else if" branches are mapped to additional AST_CONDs in the parent; b) Reverse the "direction" of the test: the constant 1 (true) is provided in the AST_CASE node, and the expression(s) in the if statement(s) are given in each AST_COND. This is necessary because the constant 1, being the common factor, must occupy the shared AST_CASE position. (This is handled in the parser "TOK_IF" expansion of behavioral_stmt.) Observe that: * The generated AST has not been changed for bare "if"s (those without unique/priority). This should minimise the risk of unexpected regressions. * It is possible that the flattening described in 2) a) above might affect the behaviour of expressions with side effects in "unique if" statements (consider "unique if( a ) ...; else if( b++ ) ...": if a is true, is b incremented?). While it might be possible to provide precise semantics here, IEEE 1800-2012 12.4.2 seems to be deliberately vague ("In unique-if and unique0-if, the conditions may be evaluated and compared in any order[...] The presence of side effects in conditions may cause nondeterministic results.") and so it seems doubtful that there is benefit in Yosys providing stronger promises on the interpretation of questionable code. --- docs/source/yosys_internals/verilog.rst | 5 +-- frontends/verilog/verilog_parser.y | 44 ++++++++++++++++++------- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/docs/source/yosys_internals/verilog.rst b/docs/source/yosys_internals/verilog.rst index eef215e5d..128280c06 100644 --- a/docs/source/yosys_internals/verilog.rst +++ b/docs/source/yosys_internals/verilog.rst @@ -377,7 +377,4 @@ from SystemVerilog: - Assignments within expressions are supported. - The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are - accepted on ``if`` and ``case`` conditionals. (Those keywords are currently - handled in the same way as their equivalent ``full_case`` and - ``parallel_case`` attributes on ``case`` statements, and checked - for syntactic validity but otherwise ignored on ``if`` statements.) + supported on ``if`` and ``case`` conditionals. diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e70542a92..485b5391c 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2872,16 +2872,34 @@ behavioral_stmt: ast_stack.pop_back(); } | if_attr TOK_IF '(' expr ')' { - AstNode *node = new AstNode(AST_CASE); + AstNode *node = 0; + AstNode *context = ast_stack.back(); + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) { + AstNode *outer = ast_stack[ast_stack.size() - 2]; + log_assert (outer && outer->type == AST_CASE); + if (outer->get_bool_attribute(ID::parallel_case)) { + // parallel "else if": append condition to outer "if" + node = outer; + log_assert (node->children.size()); + delete node->children.back(); + node->children.pop_back(); + } else if (outer->get_bool_attribute(ID::full_case)) + (*$1)[ID::full_case] = AstNode::mkconst_int(1, false); + } + AstNode *expr = new AstNode(AST_REDUCE_BOOL, $4); + if (!node) { + // not parallel "else if": begin new construction + node = new AstNode(AST_CASE); + append_attr(node, $1); + ast_stack.back()->children.push_back(node); + node->children.push_back(node->get_bool_attribute(ID::parallel_case) ? AstNode::mkconst_int(1, false, 1) : expr); + } AstNode *block = new AstNode(AST_BLOCK); - AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block); + AstNode *cond = new AstNode(AST_COND, node->get_bool_attribute(ID::parallel_case) ? expr : AstNode::mkconst_int(1, false, 1), block); SET_AST_NODE_LOC(cond, @4, @4); - ast_stack.back()->children.push_back(node); - node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4)); node->children.push_back(cond); ast_stack.push_back(node); ast_stack.push_back(block); - append_attr(node, $1); } behavioral_stmt { SET_AST_NODE_LOC(ast_stack.back(), @7, @7); } optional_else { @@ -2907,21 +2925,25 @@ if_attr: } | attr TOK_UNIQUE0 { AstNode *context = ast_stack.back(); - if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) ) + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) frontend_verilog_yyerror("unique0 keyword cannot be used for 'else if' branch."); - $$ = $1; // accept unique0 keyword, but ignore it for now + (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false); + $$ = $1; } | attr TOK_PRIORITY { AstNode *context = ast_stack.back(); - if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) ) + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) frontend_verilog_yyerror("priority keyword cannot be used for 'else if' branch."); - $$ = $1; // accept priority keyword, but ignore it for now + (*$1)[ID::full_case] = AstNode::mkconst_int(1, false); + $$ = $1; } | attr TOK_UNIQUE { AstNode *context = ast_stack.back(); - if( context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if) ) + if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) frontend_verilog_yyerror("unique keyword cannot be used for 'else if' branch."); - $$ = $1; // accept unique keyword, but ignore it for now + (*$1)[ID::full_case] = AstNode::mkconst_int(1, false); + (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false); + $$ = $1; }; case_attr: From 7b09dc31af5ca7319ec41b2c1e91dde44a5dce42 Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Thu, 29 May 2025 20:43:41 -0600 Subject: [PATCH 03/30] tests: add cases covering full_case and parallel_case semantics This is @KrystalDelusion's suggestion in PR #5141 to verify sensible implementation of all 4 possible full_case/parallel_case combinations. (Also including two similar tests to check the Verilog frontend applies the correct attributes when given SystemVerilog priority/unique case and if statements.) --- tests/proc/case_attr.ys | 57 +++++++++++++++++++++++++++ tests/verilog/unique_priority_case.ys | 54 +++++++++++++++++++++++++ tests/verilog/unique_priority_if.ys | 54 +++++++++++++++++++++++++ 3 files changed, 165 insertions(+) create mode 100644 tests/proc/case_attr.ys create mode 100644 tests/verilog/unique_priority_case.ys create mode 100644 tests/verilog/unique_priority_if.ys diff --git a/tests/proc/case_attr.ys b/tests/proc/case_attr.ys new file mode 100644 index 000000000..63be79fe5 --- /dev/null +++ b/tests/proc/case_attr.ys @@ -0,0 +1,57 @@ +read_verilog -sv << EOF +module top (input A, B, C, D, E, F, output reg W, X, Y, Z); + always @* begin + W = F; + (* full_case *) + case (C) + A: W = D; + B: W = E; + endcase + end + + always @* begin + X = F; + case (C) + A: X = D; + B: X = E; + endcase + end + + always @* begin + Y = F; + (* full_case, parallel_case *) + case (C) + A: Y = D; + B: Y = E; + endcase + end + + always @* begin + Z = F; + (* parallel_case *) + case (C) + A: Z = D; + B: Z = E; + endcase + end +endmodule +EOF +prep +# For the ones which use full_case, the F signal shouldn't be included in +# the input cone of W and Y. +select -set full o:W o:Y %u %ci* +select -assert-none i:F @full %i +select -assert-count 1 o:X %ci* i:F %i +select -assert-count 1 o:Z %ci* i:F %i + +# And for parallel_case there should be 1 $pmux compared to the 2 $mux +# cells without. +select -assert-none o:W %ci* t:$pmux %i +select -assert-none o:X %ci* t:$pmux %i +select -assert-count 1 o:Y %ci* t:$pmux %i +select -assert-count 1 o:Z %ci* t:$pmux %i + +select -assert-count 2 o:W %ci* t:$mux %i +select -assert-count 2 o:X %ci* t:$mux %i +select -assert-none o:Y %ci* t:$mux %i +select -assert-none o:Z %ci* t:$mux %i diff --git a/tests/verilog/unique_priority_case.ys b/tests/verilog/unique_priority_case.ys new file mode 100644 index 000000000..1f87fb19c --- /dev/null +++ b/tests/verilog/unique_priority_case.ys @@ -0,0 +1,54 @@ +read_verilog -sv << EOF +module top (input A, B, C, D, E, F, output reg W, X, Y, Z); + always_comb begin + W = F; + priority case (C) + A: W = D; + B: W = E; + endcase + end + + always_comb begin + X = F; + case (C) + A: X = D; + B: X = E; + endcase + end + + always_comb begin + Y = F; + unique case (C) + A: Y = D; + B: Y = E; + endcase + end + + always_comb begin + Z = F; + unique0 case (C) + A: Z = D; + B: Z = E; + endcase + end +endmodule +EOF +prep +# For the ones which use priority/unique, the F signal shouldn't be included in +# the input cone of W and Y. +select -set full o:W o:Y %u %ci* +select -assert-none i:F @full %i +select -assert-count 1 o:X %ci* i:F %i +select -assert-count 1 o:Z %ci* i:F %i + +# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux +# cells without. +select -assert-none o:W %ci* t:$pmux %i +select -assert-none o:X %ci* t:$pmux %i +select -assert-count 1 o:Y %ci* t:$pmux %i +select -assert-count 1 o:Z %ci* t:$pmux %i + +select -assert-count 2 o:W %ci* t:$mux %i +select -assert-count 2 o:X %ci* t:$mux %i +select -assert-none o:Y %ci* t:$mux %i +select -assert-none o:Z %ci* t:$mux %i diff --git a/tests/verilog/unique_priority_if.ys b/tests/verilog/unique_priority_if.ys new file mode 100644 index 000000000..a6053e809 --- /dev/null +++ b/tests/verilog/unique_priority_if.ys @@ -0,0 +1,54 @@ +read_verilog -sv << EOF +module top (input A, B, C, D, E, F, output reg W, X, Y, Z); + always_comb begin + W = F; + priority if (C == A) + W = D; + else if (C == B) + W = E; + end + + always_comb begin + X = F; + if (C == A) + X = D; + else if (C == B) + X = E; + end + + always_comb begin + Y = F; + unique if (C == A) + Y = D; + else if (C == B) + Y = E; + end + + always_comb begin + Z = F; + unique0 if (C == A) + Z = D; + else if (C == B) + Z = E; + end +endmodule +EOF +prep +# For the ones which use priority/unique, the F signal shouldn't be included in +# the input cone of W and Y. +select -set full o:W o:Y %u %ci* +select -assert-none i:F @full %i +select -assert-count 1 o:X %ci* i:F %i +select -assert-count 1 o:Z %ci* i:F %i + +# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux +# cells without. +select -assert-none o:W %ci* t:$pmux %i +select -assert-none o:X %ci* t:$pmux %i +select -assert-count 1 o:Y %ci* t:$pmux %i +select -assert-count 1 o:Z %ci* t:$pmux %i + +select -assert-count 2 o:W %ci* t:$mux %i +select -assert-count 2 o:X %ci* t:$mux %i +select -assert-none o:Y %ci* t:$mux %i +select -assert-none o:Z %ci* t:$mux %i From 62660b221f7e106dd3d966775a49f96fe65e2248 Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Fri, 30 May 2025 21:13:20 -0600 Subject: [PATCH 04/30] docs: restore and update the note about if/case attributes. --- docs/source/yosys_internals/verilog.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/yosys_internals/verilog.rst b/docs/source/yosys_internals/verilog.rst index 128280c06..0039aaab7 100644 --- a/docs/source/yosys_internals/verilog.rst +++ b/docs/source/yosys_internals/verilog.rst @@ -377,4 +377,7 @@ from SystemVerilog: - Assignments within expressions are supported. - The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are - supported on ``if`` and ``case`` conditionals. + supported on ``if`` and ``case`` conditionals. (The Verilog frontend + will process conditionals using these keywords by annotating their + representation with the appropriate ``full_case`` and/or ``parallel_case`` + attributes, which are described above.) From 10bb0f472fd2ccd6e28b63e20189ce1922ec7ceb Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Fri, 30 May 2025 21:43:33 -0600 Subject: [PATCH 05/30] docs: mention related effects for multiplexers in the cell library. --- docs/source/cell/word_mux.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/source/cell/word_mux.rst b/docs/source/cell/word_mux.rst index 3eca310f3..234d1016b 100644 --- a/docs/source/cell/word_mux.rst +++ b/docs/source/cell/word_mux.rst @@ -24,8 +24,8 @@ are zero, the value from ``A`` input is sent to the output. If the :math:`n`\ 'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of the ``B`` input is sent to the output. When more than one bit from ``S`` is set the output is undefined. Cells of this type are used to model "parallel cases" -(defined by using the ``parallel_case`` attribute or detected by an -optimization). +(defined by using the ``parallel_case`` attribute, the ``unique`` or ``unique0`` +SystemVerilog keywords, or detected by an optimization). The `$tribuf` cell is used to implement tristate logic. Cells of this type have a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A`` From ca7d94af9953f372da0a3e77780f8b3c2f873440 Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Sat, 31 May 2025 22:38:44 -0600 Subject: [PATCH 06/30] verilog: improve string literal matching speed (fixes #5076) Use a greedy regular expression to match input inside a string literal, so that flex can accumulate a longer match instead of invoking a rule for each individual character. --- frontends/verilog/verilog_lexer.l | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8a3734302..8148748d8 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s } \" { BEGIN(STRING); } -\\. { yymore(); real_location = old_location; } +([^\"]|\\.)+ { yymore(); real_location = old_location; } \" { BEGIN(0); char *yystr = strdup(yytext); @@ -376,7 +376,6 @@ TIME_SCALE_SUFFIX [munpf]?s free(yystr); return TOK_STRING; } -. { yymore(); real_location = old_location; } and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { yylval->string = new std::string(yytext); From 784de0f6e3cdac8e68f0f0685b4f4e9de4ba433d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 4 Jun 2025 08:01:21 +0200 Subject: [PATCH 07/30] Make attrmap able to alter memory attributes as well --- passes/techmap/attrmap.cc | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 96e65ff2e..58f5a47e5 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -270,26 +270,19 @@ struct AttrmapPass : public Pass { { for (auto module : design->selected_modules()) { - for (auto wire : module->selected_wires()) + for (auto wire : module->selected_members()) attrmap_apply(stringf("%s.%s", log_id(module), log_id(wire)), actions, wire->attributes); - for (auto cell : module->selected_cells()) - attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes); - - for (auto proc : module->processes) + for (auto proc : module->selected_processes()) { - if (!design->selected(module, proc.second)) - continue; - attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes); - - std::vector all_cases = {&proc.second->root_case}; + std::vector all_cases = {&proc->root_case}; while (!all_cases.empty()) { RTLIL::CaseRule *cs = all_cases.back(); all_cases.pop_back(); - attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes); + attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc)), actions, cs->attributes); for (auto &sw : cs->switches) { - attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes); + attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc)), actions, sw->attributes); all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end()); } } From 19cdbc5a0ced3b02cddf6bba227c7901d9fbbf99 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 4 Jun 2025 21:02:21 +0100 Subject: [PATCH 08/30] opt_dff: don't remove cells until all have been visited to prevent UAF --- passes/opt/opt_dff.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 8539432c0..726516fea 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -737,6 +737,7 @@ struct OptDffWorker bool run_constbits() { ModWalker modwalker(module->design, module); QuickConeSat qcsat(modwalker); + std::vector cells_to_remove; // Run as a separate sub-pass, so that we don't mutate (non-FF) cells under ModWalker. bool did_something = false; @@ -830,7 +831,7 @@ struct OptDffWorker if (!removed_sigbits.count(i)) keep_bits.push_back(i); if (keep_bits.empty()) { - module->remove(cell); + cells_to_remove.emplace_back(cell); did_something = true; continue; } @@ -840,6 +841,8 @@ struct OptDffWorker did_something = true; } } + for (auto* cell : cells_to_remove) + module->remove(cell); return did_something; } }; From 239c265093d9ca3715de6a69d59ed6cbd095a3b3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 5 Jun 2025 10:58:06 +0200 Subject: [PATCH 09/30] splitnets: handle single-bit vectors consistently --- passes/cmds/splitnets.cc | 6 +++++- tests/various/splitnets.ys | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 tests/various/splitnets.ys diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index bd8b9ceac..9e606dee1 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -207,8 +207,12 @@ struct SplitnetsPass : public Pass { else { for (auto wire : module->wires()) { - if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire)) + if (((wire->width > 1) || (wire->has_attribute(ID::single_bit_vector))) + && (wire->port_id == 0 || flag_ports) + && design->selected(module, wire)) { + wire->attributes.erase(ID::single_bit_vector); worker.splitmap[wire] = std::vector(); + } } for (auto &it : worker.splitmap) diff --git a/tests/various/splitnets.ys b/tests/various/splitnets.ys new file mode 100644 index 000000000..29652d508 --- /dev/null +++ b/tests/various/splitnets.ys @@ -0,0 +1,32 @@ +read_verilog < Date: Fri, 6 Jun 2025 23:46:07 +0100 Subject: [PATCH 10/30] opt_dff: don't emit cells until all have been visited to prevent UAF --- passes/opt/opt_dff.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 726516fea..4ed4b0cb6 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -737,9 +737,12 @@ struct OptDffWorker bool run_constbits() { ModWalker modwalker(module->design, module); QuickConeSat qcsat(modwalker); - std::vector cells_to_remove; - // Run as a separate sub-pass, so that we don't mutate (non-FF) cells under ModWalker. + // Defer mutating cells by removing them/emiting new flip flops so that + // cell references in modwalker are not invalidated + std::vector cells_to_remove; + std::vector ffs_to_emit; + bool did_something = false; for (auto cell : module->selected_cells()) { if (!RTLIL::builtin_ff_cell_types().count(cell->type)) @@ -837,12 +840,14 @@ struct OptDffWorker } ff = ff.slice(keep_bits); ff.cell = cell; - ff.emit(); + ffs_to_emit.emplace_back(ff); did_something = true; } } for (auto* cell : cells_to_remove) module->remove(cell); + for (auto& ff : ffs_to_emit) + ff.emit(); return did_something; } }; From 7160c9180051b49b5a5a9c0559c3d6cb469f089a Mon Sep 17 00:00:00 2001 From: George Rennie Date: Fri, 6 Jun 2025 23:46:23 +0100 Subject: [PATCH 11/30] tests: add test for #5164 opt_dff -sat UAF --- tests/opt/bug5164.ys | 60 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 tests/opt/bug5164.ys diff --git a/tests/opt/bug5164.ys b/tests/opt/bug5164.ys new file mode 100644 index 000000000..4ee71fe45 --- /dev/null +++ b/tests/opt/bug5164.ys @@ -0,0 +1,60 @@ +read_rtlil < Date: Sat, 7 Jun 2025 22:21:09 +0800 Subject: [PATCH 12/30] Allows calling yosys_shutdown and then yosys_setup to restart. --- kernel/yosys.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7d0d688fc..196b78186 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -187,12 +187,14 @@ int run_command(const std::string &command, std::function Date: Mon, 9 Jun 2025 19:07:53 +0200 Subject: [PATCH 13/30] Update CI, windows-2019 is deprecated --- .github/workflows/extra-builds.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 0c3146e41..d7ceb3fe3 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -36,7 +36,7 @@ jobs: vs-build: name: Visual Studio build - runs-on: windows-2019 + runs-on: windows-latest needs: [vs-prep, pre_job] if: needs.pre_job.outputs.should_skip != 'true' steps: From c561ba84e37991ff9f1d4404308d4d5d6f06ec25 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 10 Jun 2025 00:24:41 +0000 Subject: [PATCH 14/30] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b53526039..caa808a3a 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+0 +YOSYS_VER := 0.54+1 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 4ade617c41487ac4b6ab4ccc57b8d3bdb6cef158 Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 13 Jun 2025 10:31:53 +1200 Subject: [PATCH 15/30] driver.cc: Don't split options on commas --- kernel/driver.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/driver.cc b/kernel/driver.cc index 9acc58dc4..76c11853e 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -20,6 +20,7 @@ #include "kernel/yosys.h" #include "kernel/hashlib.h" #include "libs/sha1/sha1.h" +#define CXXOPTS_VECTOR_DELIMITER '\0' #include "libs/cxxopts/include/cxxopts.hpp" #include From f019e44e74e33ea48c8039c86cf69d841a13a3c3 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 13 Jun 2025 21:27:31 +0200 Subject: [PATCH 16/30] verificsva: Support the followed-by operator in cover mode The implementation for the implication operator in cover mode actually implements the followed-by operator, so we can re-use it unchanged. It is not always the correct behavior for the implication operator in cover mode, but a) it will only cause false positives not miss anything so if the behavior is unexpected it will be visible in the produced traces, b) it is unlikely to make a difference for most properties one would practically use in cover mode, c) at least one other widely used SVA implementations behaves the same way and d) it's not clear whether we can fix this without rewriting most of verificsva.cc --- frontends/verific/verificsva.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 860d3c166..7652f8130 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1613,7 +1613,10 @@ struct VerificSvaImporter } else if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION || - inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) + inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || + (mode_cover && ( + inst->Type() == PRIM_SVA_OVERLAPPED_FOLLOWED_BY || + inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION))) { Net *antecedent_net = inst->GetInput1(); Net *consequent_net = inst->GetInput2(); @@ -1621,7 +1624,7 @@ struct VerificSvaImporter SvaFsm antecedent_fsm(clocking, trig); node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net); - if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) { + if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || inst->Type() == PRIM_SVA_NON_OVERLAPPED_FOLLOWED_BY) { int next_node = antecedent_fsm.createNode(); antecedent_fsm.createEdge(node, next_node); node = next_node; From cd71f190cd8c24748432abe1071f84609b589d9c Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 14 Jun 2025 00:24:06 +0000 Subject: [PATCH 17/30] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index caa808a3a..b452105b1 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+1 +YOSYS_VER := 0.54+15 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 834a7294b7c790612e9d1a686b374130b43d814e Mon Sep 17 00:00:00 2001 From: garytwong Date: Thu, 19 Jun 2025 16:41:18 +0000 Subject: [PATCH 18/30] verilog: fix string literal regular expression (#5187) * verilog: fix string literal regular expression. A backslash was improperly quoted, causing string literal matching to fail when the final token before a closing quote was an escaped backslash. * verilog: add regression test for string literal regex bug. Test for bug triggered by escaped backslash immediately before closing quote (introduced in ca7d94af and fixed by 40aa7eaf). --- frontends/verilog/verilog_lexer.l | 2 +- tests/verilog/bug5160.v | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) create mode 100644 tests/verilog/bug5160.v diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8148748d8..40162b8d3 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s } \" { BEGIN(STRING); } -([^\"]|\\.)+ { yymore(); real_location = old_location; } +([^\\"]|\\.)+ { yymore(); real_location = old_location; } \" { BEGIN(0); char *yystr = strdup(yytext); diff --git a/tests/verilog/bug5160.v b/tests/verilog/bug5160.v new file mode 100644 index 000000000..5b141a360 --- /dev/null +++ b/tests/verilog/bug5160.v @@ -0,0 +1,5 @@ +// Regression test for bug mentioned in #5160: +// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084 +module top; + initial $display( "\\" ); +endmodule From 44aa313ba976b68476aaa3d548098d7f54e61094 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 20 Jun 2025 00:24:40 +0000 Subject: [PATCH 19/30] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b452105b1..e742928b3 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+15 +YOSYS_VER := 0.54+17 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From beaca05b405c9547375358df9a86a6193e80902d Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 21 Jun 2025 09:49:56 +1200 Subject: [PATCH 20/30] Include boxes in attrmap Rename `selected_members` iterator to memb. Add comment on `selected_processes` loop for clarity. --- passes/techmap/attrmap.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 58f5a47e5..7f5bfc94f 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -263,16 +263,17 @@ struct AttrmapPass : public Pass { if (modattr_mode) { - for (auto module : design->selected_whole_modules()) + for (auto module : design->all_selected_whole_modules()) attrmap_apply(stringf("%s", log_id(module)), actions, module->attributes); } else { - for (auto module : design->selected_modules()) + for (auto module : design->all_selected_modules()) { - for (auto wire : module->selected_members()) - attrmap_apply(stringf("%s.%s", log_id(module), log_id(wire)), actions, wire->attributes); + for (auto memb : module->selected_members()) + attrmap_apply(stringf("%s.%s", log_id(module), log_id(memb)), actions, memb->attributes); + // attrmap already applied to process itself during above loop, but not its children for (auto proc : module->selected_processes()) { std::vector all_cases = {&proc->root_case}; From 34a2abeddb5054df29140baf1c6d5af02a9aac63 Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Fri, 20 Jun 2025 17:26:20 -0600 Subject: [PATCH 21/30] verilog: fix parser "if" memory errors. Fix buggy memory allocation introduced in #5152: 1) clean up ast_stack to reflect AST node rearrangement when necessary, to avoid dangling pointer; 2) call free_attr() on unused attribute list when no new syntax node is created, to avoid leaking it. --- frontends/verilog/verilog_parser.y | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 7e53005f3..17edc357d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2874,6 +2874,7 @@ behavioral_stmt: } | if_attr TOK_IF '(' expr ')' { AstNode *node = 0; + AstNode *block = new AstNode(AST_BLOCK); AstNode *context = ast_stack.back(); if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) { AstNode *outer = ast_stack[ast_stack.size() - 2]; @@ -2882,8 +2883,10 @@ behavioral_stmt: // parallel "else if": append condition to outer "if" node = outer; log_assert (node->children.size()); + ast_stack.pop_back(); delete node->children.back(); node->children.pop_back(); + ast_stack.push_back(block); } else if (outer->get_bool_attribute(ID::full_case)) (*$1)[ID::full_case] = AstNode::mkconst_int(1, false); } @@ -2894,8 +2897,8 @@ behavioral_stmt: append_attr(node, $1); ast_stack.back()->children.push_back(node); node->children.push_back(node->get_bool_attribute(ID::parallel_case) ? AstNode::mkconst_int(1, false, 1) : expr); - } - AstNode *block = new AstNode(AST_BLOCK); + } else + free_attr($1); AstNode *cond = new AstNode(AST_COND, node->get_bool_attribute(ID::parallel_case) ? expr : AstNode::mkconst_int(1, false, 1), block); SET_AST_NODE_LOC(cond, @4, @4); node->children.push_back(cond); From a0a77cd1d0b8710e8bbfb6f3188b5d43bdaf44fd Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 24 Jun 2025 00:24:55 +0000 Subject: [PATCH 22/30] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e742928b3..77771b6b0 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+17 +YOSYS_VER := 0.54+23 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From e6961d8c9ff181771c57a11cae116470176c6629 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 28 Jun 2025 11:33:18 +1200 Subject: [PATCH 23/30] CI: Test with ASAN as well New matrix variable for sanitizer, running `undefined` and `address` separately (because they are mutually exclusive). Probably don't need to run both sanitizers on both os targets, but it's probably fine. --- .github/workflows/test-build.yml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index b88662f0f..22d3a94f8 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -40,6 +40,7 @@ jobs: strategy: matrix: os: [ubuntu-latest, macos-latest] + sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -57,7 +58,7 @@ jobs: mkdir build cd build make -f ../Makefile config-$CC - echo 'SANITIZER = undefined' >> Makefile.conf + echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf make -f ../Makefile -j$procs ENABLE_LTO=1 - name: Log yosys-config output @@ -73,7 +74,7 @@ jobs: - name: Store build artifact uses: actions/upload-artifact@v4 with: - name: build-${{ matrix.os }} + name: build-${{ matrix.os }}-${{ matrix.sanitizer }} path: build.tar retention-days: 1 @@ -84,10 +85,12 @@ jobs: if: needs.pre_job.outputs.should_skip != 'true' env: CC: clang + ASAN_OPTIONS: halt_on_error=1 UBSAN_OPTIONS: halt_on_error=1 strategy: matrix: os: [ubuntu-latest, macos-latest] + sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -136,7 +139,7 @@ jobs: - name: Download build artifact uses: actions/download-artifact@v4 with: - name: build-${{ matrix.os }} + name: build-${{ matrix.os }}-${{ matrix.sanitizer }} - name: Uncompress build shell: bash @@ -168,6 +171,7 @@ jobs: strategy: matrix: os: [ubuntu-latest] + sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -181,7 +185,7 @@ jobs: - name: Download build artifact uses: actions/download-artifact@v4 with: - name: build-${{ matrix.os }} + name: build-${{ matrix.os }}-${{ matrix.sanitizer }} - name: Uncompress build shell: bash From 017524d7a2a1a170b1f22ae3df996b3b4ce875d6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 28 Jun 2025 11:33:18 +1200 Subject: [PATCH 24/30] tests/verific: Don't ASAN verific --- tests/verific/run-test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/verific/run-test.sh b/tests/verific/run-test.sh index dee032827..2e340916d 100755 --- a/tests/verific/run-test.sh +++ b/tests/verific/run-test.sh @@ -2,3 +2,4 @@ set -eu source ../gen-tests-makefile.sh generate_mk --yosys-scripts --bash +sed -i '1i\export ASAN_OPTIONS=halt_on_error=0' run-test.mk From 67583fee48be2428781f86e323c21886054559cb Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 30 Jun 2025 00:27:10 +0000 Subject: [PATCH 25/30] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 77771b6b0..3c2bc11b6 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+23 +YOSYS_VER := 0.54+29 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 85e7c68fc60d785b743851e0233f8430c61865a3 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Wed, 2 Jul 2025 12:39:18 +1000 Subject: [PATCH 26/30] Gowin. BUGFIX. Fix multi-line descriptions. If let's say the enumeration of inputs took several lines, then all after the first one were ignored. Since the first line ended with a comma, an error was generated when trying to use the resulting file. Signed-off-by: YRabbit --- techlibs/gowin/cells_xtra.py | 10 + techlibs/gowin/cells_xtra_gw5a.v | 601 +++++++++++++++++++++++++++++-- 2 files changed, 585 insertions(+), 26 deletions(-) diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py index be2e0eff3..7a7c9ac0a 100644 --- a/techlibs/gowin/cells_xtra.py +++ b/techlibs/gowin/cells_xtra.py @@ -11,6 +11,7 @@ import re class State(Enum): OUTSIDE = auto() IN_MODULE = auto() + IN_MODULE_MULTILINE = auto() IN_PARAMETER = auto() _skip = { # These are already described, no need to extract them from the vendor files @@ -47,12 +48,20 @@ def xtract_cells_decl(dir, fout): fout.write(l) if l[-1] != '\n': fout.write('\n') + if l.rstrip()[-1] != ';': + state = State.IN_MODULE_MULTILINE elif l.startswith('parameter') and state == State.IN_MODULE: fout.write(l) if l.rstrip()[-1] == ',': state = State.IN_PARAMETER if l[-1] != '\n': fout.write('\n') + elif l and state == State.IN_MODULE_MULTILINE: + fout.write(l) + if l[-1] != '\n': + fout.write('\n') + if l.rstrip()[-1] == ';': + state = State.IN_MODULE elif state == State.IN_PARAMETER: fout.write(l) if l.rstrip()[-1] == ';': @@ -65,6 +74,7 @@ def xtract_cells_decl(dir, fout): if l[-1] != '\n': fout.write('\n') + if __name__ == '__main__': parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.') parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/') diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v index d19435f85..c82f6af25 100644 --- a/techlibs/gowin/cells_xtra_gw5a.v +++ b/techlibs/gowin/cells_xtra_gw5a.v @@ -80,19 +80,8 @@ endmodule module MIPI_OBUF_A (...); output O, OB; input I, IB, IL, MODESEL; -endmodule - -module IBUF_R (...); -input I; -input RTEN; -output O; -endmodule - -module IOBUF_R (...); -input I,OEN; -input RTEN; -output O; -inout IO; +inout IO, IOB; +input OEN, OENB; endmodule module ELVDS_IOBUF_R (...); @@ -113,6 +102,21 @@ input I, IB; input ADCEN; endmodule +module MIPI_CPHY_IBUF (...); +output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2; +inout IO0, IOB0, IO1, IOB1, IO2, IOB2; +input I0, IB0, I1, IB1, I2, IB2; +input OEN, OENB; +input HSEN; +endmodule + +module MIPI_CPHY_OBUF (...); +output O0, OB0, O1, OB1, O2, OB2; +input I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2; +inout IO0, IOB0, IO1, IOB1, IO2, IOB2; +input OEN, OENB, MODESEL, VCOME; +endmodule + module SDPB (...); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; @@ -598,8 +602,8 @@ endmodule module SDP36KE (...); -parameter ECC_WRITE_EN="FALSE"; -parameter ECC_READ_EN="FALSE"; +parameter ECC_WRITE_EN="TRUE"; +parameter ECC_READ_EN="TRUE"; parameter READ_MODE = 1'b0; parameter BLK_SEL_A = 3'b000; parameter BLK_SEL_B = 3'b000; @@ -764,6 +768,14 @@ output [7:0] ECCP; endmodule +module SDP136K (...); +input CLKA, CLKB; +input WE, RE; +input [10:0] ADA, ADB; +input [67:0] DI; +output [67:0] DO; +endmodule + module MULTADDALU12X12 (...); parameter A0REG_CLK = "BYPASS"; parameter A0REG_CE = "CE0"; @@ -980,6 +992,24 @@ input PSEL; input PADDSUB; endmodule +module MULTACC (...); +output [23:0] DATAO, CASO; +input CE, CLK; +input [5:0] COFFIN0, COFFIN1, COFFIN2; +input [9:0] DATAIN0, DATAIN1; +input [9:0] DATAIN2; +input RSTN; +input [23:0] CASI; +parameter COFFIN_WIDTH = 4; +parameter DATAIN_WIDTH = 8; +parameter IREG = 1'b0; +parameter OREG = 1'b0; +parameter PREG = 1'b0; +parameter ACC_EN = "FALSE"; +parameter CASI_EN = "FALSE"; +parameter CASO_EN = "FALSE"; +endmodule + module IDDR_MEM (...); input D, ICLK, PCLK; input [2:0] WADDR; @@ -1048,6 +1078,12 @@ output Q0, Q1; endmodule +module OSER14 (...); +input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13; +input PCLK, FCLK, RESET; +output Q; +endmodule + module IODELAY (...); parameter C_STATIC_DLY = 0; parameter DYN_DLY_EN = "FALSE"; @@ -1066,13 +1102,39 @@ output [31:0] Q; input D; input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; input RESET; -output DF; -input SDTAP; -input VALUE; -input [7:0] DLYSTEP; -parameter C_STATIC_DLY = 0; -parameter DYN_DLY_EN = "FALSE"; -parameter ADAPT_EN = "FALSE"; +output DF0, DF1; +input SDTAP0, SDTAP1; +input VALUE0,VALUE1; +input [7:0] DLYSTEP0,DLYSTEP1; +parameter C_STATIC_DLY_0 = 0; +parameter DYN_DLY_EN_0 = "FALSE"; +parameter ADAPT_EN_0 = "FALSE"; +parameter C_STATIC_DLY_1 = 0; +parameter DYN_DLY_EN_1 = "FALSE"; +parameter ADAPT_EN_1 = "FALSE"; +endmodule + +module OSIDES64 (...); +output [63:0] Q; +input D; +input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; +input RESET; +output DF0, DF1, DF2, DF3; +input SDTAP0, SDTAP1, SDTAP2, SDTAP3; +input VALUE0, VALUE1, VALUE2, VALUE3; +input [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3; +parameter C_STATIC_DLY_0 = 0; +parameter DYN_DLY_EN_0 = "FALSE"; +parameter ADAPT_EN_0 = "FALSE"; +parameter C_STATIC_DLY_1 = 0; +parameter DYN_DLY_EN_1 = "FALSE"; +parameter ADAPT_EN_1 = "FALSE"; +parameter C_STATIC_DLY_2 = 0; +parameter DYN_DLY_EN_2 = "FALSE"; +parameter ADAPT_EN_2 = "FALSE"; +parameter C_STATIC_DLY_3 = 0; +parameter DYN_DLY_EN_3 = "FALSE"; +parameter ADAPT_EN_3 = "FALSE"; endmodule module DCE (...); @@ -1132,6 +1194,17 @@ output OSCOUT; input OSCEN; endmodule +module OSCB (...); +parameter FREQ_MODE = "25"; +parameter FREQ_DIV = 10; +parameter DYN_TRIM_EN = "FALSE"; +output OSCOUT; +output OSCREF; +input OSCEN, FMODE; +input [7:0] RTRIM; +input [5:0] RTCTRIM; +endmodule + module PLL (...); input CLKIN; input CLKFB; @@ -1571,8 +1644,8 @@ input ADWSEL; endmodule module OTP (...); -parameter MODE = 1'b0; -input READ, SHIFT; +parameter MODE = 2'b01; +input CLK, READ, SHIFT; output DOUT; endmodule @@ -1615,6 +1688,31 @@ input ERR0INJECT,ERR1INJECT; input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule +module CMSERB (...); +output RUNNING; +output CRCERR; +output CRCDONE; +output ECCCORR; +output ECCUNCORR; +output [12:0] ERRLOC; +output ECCDEC; +output DSRRD; +output DSRWR; +output ASRRESET; +output ASRINC; +output REFCLK; +input CLK; +input [2:0] SEREN; +input ERR0INJECT,ERR1INJECT; +input [6:0] ERRINJ0LOC,ERRINJ1LOC; +endmodule + +module SAMBA (...); +parameter MODE = 2'b00; +input SPIAD; +input LOAD; +endmodule + module ADCLRC (...); endmodule @@ -1624,6 +1722,12 @@ endmodule module ADC (...); endmodule +module ADC_SAR (...); +endmodule + +module LICD (...); +endmodule + module MIPI_DPHY (...); output RX_CLK_O, TX_CLK_O; output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; @@ -1632,6 +1736,7 @@ input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN; output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P; inout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P; input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, + LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK; input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X; input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN; input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; @@ -1639,6 +1744,8 @@ input HSTXD_VLD; input CK0, CK90, CK180, CK270; input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, + HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; output [7:0] MRDATA; input MA_INC, MCLK; @@ -1714,7 +1821,7 @@ parameter RX_RD_START_DEPTH = 5'b00001; parameter RX_SYNC_MODE = 1'b0 ; parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; -parameter RX_WORD_LITTLE_ENDIAN = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; parameter TX_BYPASS_MODE = 1'b0 ; parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; parameter TX_OCLK_USE_CIBCLK = 1'b0 ; @@ -1917,6 +2024,437 @@ parameter TEST_P_IMP_LN3 = 1'b0 ; parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule +module MIPI_DPHYA (...); +output RX_CLK_O, TX_CLK_O; +output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; +output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; +input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN; +output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P; +inout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P; +input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, + LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK; +input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X; +input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN; +input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; +input HSTXD_VLD; +input CK0, CK90, CK180, CK270; +input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; +input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, + HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; +input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; +output [7:0] MRDATA; +input MA_INC, MCLK; +input [1:0] MOPCODE; +input [7:0] MWDATA; +input SPLL_CKN, SPLL_CKP; +output ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK; +output D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE; +output D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR; +input D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ; +input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK; +input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK; +input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK; +input ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK; +parameter TX_PLLCLK = "NONE"; +parameter RX_ALIGN_BYTE = 8'b10111000 ; +parameter RX_HS_8BIT_MODE = 1'b0 ; +parameter RX_LANE_ALIGN_EN = 1'b0 ; +parameter TX_HS_8BIT_MODE = 1'b0 ; +parameter HSREG_EN_LN0 = 1'b0; +parameter HSREG_EN_LN1 = 1'b0; +parameter HSREG_EN_LN2 = 1'b0; +parameter HSREG_EN_LN3 = 1'b0; +parameter HSREG_EN_LNCK = 1'b0; +parameter LANE_DIV_SEL = 2'b00; +parameter HSRX_EN = 1'b1 ; +parameter HSRX_LANESEL = 4'b1111 ; +parameter HSRX_LANESEL_CK = 1'b1 ; +parameter HSTX_EN_LN0 = 1'b0 ; +parameter HSTX_EN_LN1 = 1'b0 ; +parameter HSTX_EN_LN2 = 1'b0 ; +parameter HSTX_EN_LN3 = 1'b0 ; +parameter HSTX_EN_LNCK = 1'b0 ; +parameter LPTX_EN_LN0 = 1'b1 ; +parameter LPTX_EN_LN1 = 1'b1 ; +parameter LPTX_EN_LN2 = 1'b1 ; +parameter LPTX_EN_LN3 = 1'b1 ; +parameter LPTX_EN_LNCK = 1'b1 ; +parameter TXDP_EN_LN0 = 1'b0 ; +parameter TXDP_EN_LN1 = 1'b0 ; +parameter TXDP_EN_LN2 = 1'b0 ; +parameter TXDP_EN_LN3 = 1'b0 ; +parameter TXDP_EN_LNCK = 1'b0 ; +parameter SPLL_DIV_SEL = 2'b00; +parameter DPHY_CK_SEL = 2'b01; +parameter CKLN_DELAY_EN = 1'b0; +parameter CKLN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DELAY_EN = 1'b0; +parameter D0LN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DESKEW_BYPASS = 1'b0; +parameter D1LN_DELAY_EN = 1'b0; +parameter D1LN_DELAY_OVR_VAL = 7'b0000000; +parameter D1LN_DESKEW_BYPASS = 1'b0; +parameter D2LN_DELAY_EN = 1'b0; +parameter D2LN_DELAY_OVR_VAL = 7'b0000000; +parameter D2LN_DESKEW_BYPASS = 1'b0; +parameter D3LN_DELAY_EN = 1'b0; +parameter D3LN_DELAY_OVR_VAL = 7'b0000000; +parameter D3LN_DESKEW_BYPASS = 1'b0; +parameter DESKEW_EN_LOW_DELAY = 1'b0; +parameter DESKEW_EN_ONE_EDGE = 1'b0; +parameter DESKEW_FAST_LOOP_TIME = 4'b0000; +parameter DESKEW_FAST_MODE = 1'b0; +parameter DESKEW_HALF_OPENING = 6'b010110; +parameter DESKEW_LSB_MODE = 2'b00; +parameter DESKEW_M = 3'b011; +parameter DESKEW_M_TH = 13'b0000110100110; +parameter DESKEW_MAX_SETTING = 7'b0100001; +parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; +parameter DESKEW_RST_BYPASS = 1'b0 ; +parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; +parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; +parameter RX_INVERT = 1'b0 ; +parameter RX_ONE_BYTE0_MATCH = 1'b0 ; +parameter RX_RD_START_DEPTH = 5'b00001; +parameter RX_SYNC_MODE = 1'b0 ; +parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; +parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter TX_BYPASS_MODE = 1'b0 ; +parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; +parameter TX_OCLK_USE_CIBCLK = 1'b0 ; +parameter TX_RD_START_DEPTH = 5'b00001; +parameter TX_SYNC_MODE = 1'b0 ; +parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter EQ_CS_LANE0 = 3'b100; +parameter EQ_CS_LANE1 = 3'b100; +parameter EQ_CS_LANE2 = 3'b100; +parameter EQ_CS_LANE3 = 3'b100; +parameter EQ_CS_LANECK = 3'b100; +parameter EQ_RS_LANE0 = 3'b100; +parameter EQ_RS_LANE1 = 3'b100; +parameter EQ_RS_LANE2 = 3'b100; +parameter EQ_RS_LANE3 = 3'b100; +parameter EQ_RS_LANECK = 3'b100; +parameter HSCLK_LANE_LN0 = 1'b0; +parameter HSCLK_LANE_LN1 = 1'b0; +parameter HSCLK_LANE_LN2 = 1'b0; +parameter HSCLK_LANE_LN3 = 1'b0; +parameter HSCLK_LANE_LNCK = 1'b1; +parameter ALP_ED_EN_LANE0 = 1'b1 ; +parameter ALP_ED_EN_LANE1 = 1'b1 ; +parameter ALP_ED_EN_LANE2 = 1'b1 ; +parameter ALP_ED_EN_LANE3 = 1'b1 ; +parameter ALP_ED_EN_LANECK = 1'b1 ; +parameter ALP_ED_TST_LANE0 = 1'b0 ; +parameter ALP_ED_TST_LANE1 = 1'b0 ; +parameter ALP_ED_TST_LANE2 = 1'b0 ; +parameter ALP_ED_TST_LANE3 = 1'b0 ; +parameter ALP_ED_TST_LANECK = 1'b0 ; +parameter ALP_EN_LN0 = 1'b0 ; +parameter ALP_EN_LN1 = 1'b0 ; +parameter ALP_EN_LN2 = 1'b0 ; +parameter ALP_EN_LN3 = 1'b0 ; +parameter ALP_EN_LNCK = 1'b0 ; +parameter ALP_HYS_EN_LANE0 = 1'b1 ; +parameter ALP_HYS_EN_LANE1 = 1'b1 ; +parameter ALP_HYS_EN_LANE2 = 1'b1 ; +parameter ALP_HYS_EN_LANE3 = 1'b1 ; +parameter ALP_HYS_EN_LANECK = 1'b1 ; +parameter ALP_TH_LANE0 = 4'b1000 ; +parameter ALP_TH_LANE1 = 4'b1000 ; +parameter ALP_TH_LANE2 = 4'b1000 ; +parameter ALP_TH_LANE3 = 4'b1000 ; +parameter ALP_TH_LANECK = 4'b1000 ; +parameter ANA_BYTECLK_PH = 2'b00 ; +parameter BIT_REVERSE_LN0 = 1'b0 ; +parameter BIT_REVERSE_LN1 = 1'b0 ; +parameter BIT_REVERSE_LN2 = 1'b0 ; +parameter BIT_REVERSE_LN3 = 1'b0 ; +parameter BIT_REVERSE_LNCK = 1'b0 ; +parameter BYPASS_TXHCLKEN = 1'b1 ; +parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; +parameter BYTE_CLK_POLAR = 1'b0 ; +parameter BYTE_REVERSE_LN0 = 1'b0 ; +parameter BYTE_REVERSE_LN1 = 1'b0 ; +parameter BYTE_REVERSE_LN2 = 1'b0 ; +parameter BYTE_REVERSE_LN3 = 1'b0 ; +parameter BYTE_REVERSE_LNCK = 1'b0 ; +parameter EN_CLKB1X = 1'b1 ; +parameter EQ_PBIAS_LANE0 = 4'b1000 ; +parameter EQ_PBIAS_LANE1 = 4'b1000 ; +parameter EQ_PBIAS_LANE2 = 4'b1000 ; +parameter EQ_PBIAS_LANE3 = 4'b1000 ; +parameter EQ_PBIAS_LANECK = 4'b1000 ; +parameter EQ_ZLD_LANE0 = 4'b1000 ; +parameter EQ_ZLD_LANE1 = 4'b1000 ; +parameter EQ_ZLD_LANE2 = 4'b1000 ; +parameter EQ_ZLD_LANE3 = 4'b1000 ; +parameter EQ_ZLD_LANECK = 4'b1000 ; +parameter HIGH_BW_LANE0 = 1'b1 ; +parameter HIGH_BW_LANE1 = 1'b1 ; +parameter HIGH_BW_LANE2 = 1'b1 ; +parameter HIGH_BW_LANE3 = 1'b1 ; +parameter HIGH_BW_LANECK = 1'b1 ; +parameter HSREG_VREF_CTL = 3'b100 ; +parameter HSREG_VREF_EN = 1'b1 ; +parameter HSRX_DLY_CTL_CK = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; +parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; +parameter HSRX_DLY_SEL_LANECK = 1'b0 ; +parameter HSRX_DUTY_LANE0 = 4'b1000 ; +parameter HSRX_DUTY_LANE1 = 4'b1000 ; +parameter HSRX_DUTY_LANE2 = 4'b1000 ; +parameter HSRX_DUTY_LANE3 = 4'b1000 ; +parameter HSRX_DUTY_LANECK = 4'b1000 ; +parameter HSRX_EQ_EN_LANE0 = 1'b1 ; +parameter HSRX_EQ_EN_LANE1 = 1'b1 ; +parameter HSRX_EQ_EN_LANE2 = 1'b1 ; +parameter HSRX_EQ_EN_LANE3 = 1'b1 ; +parameter HSRX_EQ_EN_LANECK = 1'b1 ; +parameter HSRX_IBIAS = 4'b0011 ; +parameter HSRX_IBIAS_TEST_EN = 1'b0 ; +parameter HSRX_IMARG_EN = 1'b0 ; +parameter HSRX_ODT_EN = 1'b1 ; +parameter HSRX_ODT_TST = 4'b0000 ; +parameter HSRX_ODT_TST_CK = 1'b0 ; +parameter HSRX_SEL = 4'b0000 ; +parameter HSRX_STOP_EN = 1'b0 ; +parameter HSRX_TST = 4'b0000 ; +parameter HSRX_TST_CK = 1'b0 ; +parameter HSRX_WAIT4EDGE = 1'b1 ; +parameter HYST_NCTL = 2'b01 ; +parameter HYST_PCTL = 2'b01 ; +parameter IBIAS_TEST_EN = 1'b0 ; +parameter LB_CH_SEL = 1'b0 ; +parameter LB_EN_LN0 = 1'b0 ; +parameter LB_EN_LN1 = 1'b0 ; +parameter LB_EN_LN2 = 1'b0 ; +parameter LB_EN_LN3 = 1'b0 ; +parameter LB_EN_LNCK = 1'b0 ; +parameter LB_POLAR_LN0 = 1'b0 ; +parameter LB_POLAR_LN1 = 1'b0 ; +parameter LB_POLAR_LN2 = 1'b0 ; +parameter LB_POLAR_LN3 = 1'b0 ; +parameter LB_POLAR_LNCK = 1'b0 ; +parameter LOW_LPRX_VTH = 1'b0 ; +parameter LPBK_DATA2TO1 = 4'b0000; +parameter LPBK_DATA2TO1_CK = 1'b0 ; +parameter LPBK_EN = 1'b0 ; +parameter LPBK_SEL = 4'b0000; +parameter LPBKTST_EN = 4'b0000; +parameter LPBKTST_EN_CK = 1'b0 ; +parameter LPRX_EN = 1'b1 ; +parameter LPRX_TST = 4'b0000; +parameter LPRX_TST_CK = 1'b0 ; +parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; +parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; +parameter LPTX_NIMP_LN0 = 3'b100 ; +parameter LPTX_NIMP_LN1 = 3'b100 ; +parameter LPTX_NIMP_LN2 = 3'b100 ; +parameter LPTX_NIMP_LN3 = 3'b100 ; +parameter LPTX_NIMP_LNCK = 3'b100 ; +parameter LPTX_PIMP_LN0 = 3'b100 ; +parameter LPTX_PIMP_LN1 = 3'b100 ; +parameter LPTX_PIMP_LN2 = 3'b100 ; +parameter LPTX_PIMP_LN3 = 3'b100 ; +parameter LPTX_PIMP_LNCK = 3'b100 ; +parameter MIPI_PMA_DIS_N = 1'b1 ; +parameter PGA_BIAS_LANE0 = 4'b1000 ; +parameter PGA_BIAS_LANE1 = 4'b1000 ; +parameter PGA_BIAS_LANE2 = 4'b1000 ; +parameter PGA_BIAS_LANE3 = 4'b1000 ; +parameter PGA_BIAS_LANECK = 4'b1000 ; +parameter PGA_GAIN_LANE0 = 4'b1000 ; +parameter PGA_GAIN_LANE1 = 4'b1000 ; +parameter PGA_GAIN_LANE2 = 4'b1000 ; +parameter PGA_GAIN_LANE3 = 4'b1000 ; +parameter PGA_GAIN_LANECK = 4'b1000 ; +parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; +parameter RX_ODT_TRIM_LANECK = 4'b1000 ; +parameter SLEWN_CTL_LN0 = 4'b1111 ; +parameter SLEWN_CTL_LN1 = 4'b1111 ; +parameter SLEWN_CTL_LN2 = 4'b1111 ; +parameter SLEWN_CTL_LN3 = 4'b1111 ; +parameter SLEWN_CTL_LNCK = 4'b1111 ; +parameter SLEWP_CTL_LN0 = 4'b1111 ; +parameter SLEWP_CTL_LN1 = 4'b1111 ; +parameter SLEWP_CTL_LN2 = 4'b1111 ; +parameter SLEWP_CTL_LN3 = 4'b1111 ; +parameter SLEWP_CTL_LNCK = 4'b1111 ; +parameter STP_UNIT = 2'b01 ; +parameter TERMN_CTL_LN0 = 4'b1000 ; +parameter TERMN_CTL_LN1 = 4'b1000 ; +parameter TERMN_CTL_LN2 = 4'b1000 ; +parameter TERMN_CTL_LN3 = 4'b1000 ; +parameter TERMN_CTL_LNCK = 4'b1000 ; +parameter TERMP_CTL_LN0 = 4'b1000 ; +parameter TERMP_CTL_LN1 = 4'b1000 ; +parameter TERMP_CTL_LN2 = 4'b1000 ; +parameter TERMP_CTL_LN3 = 4'b1000 ; +parameter TERMP_CTL_LNCK = 4'b1000 ; +parameter TEST_EN_LN0 = 1'b0 ; +parameter TEST_EN_LN1 = 1'b0 ; +parameter TEST_EN_LN2 = 1'b0 ; +parameter TEST_EN_LN3 = 1'b0 ; +parameter TEST_EN_LNCK = 1'b0 ; +parameter TEST_N_IMP_LN0 = 1'b0 ; +parameter TEST_N_IMP_LN1 = 1'b0 ; +parameter TEST_N_IMP_LN2 = 1'b0 ; +parameter TEST_N_IMP_LN3 = 1'b0 ; +parameter TEST_N_IMP_LNCK = 1'b0 ; +parameter TEST_P_IMP_LN0 = 1'b0 ; +parameter TEST_P_IMP_LN1 = 1'b0 ; +parameter TEST_P_IMP_LN2 = 1'b0 ; +parameter TEST_P_IMP_LN3 = 1'b0 ; +parameter TEST_P_IMP_LNCK = 1'b0 ; +endmodule + +module MIPI_CPHY (...); +output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD; +output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD; +output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD; +output D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR; +output [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA; +output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O; +output HSTX_FIFO_AE, HSTX_FIFO_AF; +output HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR; +output RX_CLK_MUXED; +output TX_CLK_1X_O; +output DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C; +output [7:0] MDRP_RDATA; +inout D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C; +input D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN; +input [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA; +input D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD; +input [1:0] D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS; +input D0LN_RX_CLK_1X_I,D1LN_RX_CLK_1X_I, D2LN_RX_CLK_1X_I; +input D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N; +input HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2; +input [7:0] MDRP_A_D_I; +input MDRP_A_INC_I; +input MDRP_CLK_I; +input [1:0] MDRP_OPCODE_I; +input PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX; +input ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; +input ARSTN_TX; +input RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; +input TX_CLK_1X_I; +input TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; +input TXHCLK_EN; +input DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2; +input GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270; +input HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; +input HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2; +input LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; +input SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP; +parameter TX_PLLCLK = "NONE"; +parameter D0LN_HS_TX_EN = 1'b1; +parameter D1LN_HS_TX_EN = 1'b1; +parameter D2LN_HS_TX_EN = 1'b1; +parameter D0LN_HS_RX_EN = 1'b1; +parameter D1LN_HS_RX_EN = 1'b1; +parameter D2LN_HS_RX_EN = 1'b1; +parameter TX_HS_21BIT_MODE = 1'b0; +parameter RX_OUTCLK_SEL = 2'b00; +parameter TX_W_LENDIAN = 1'b1; +parameter CLK_SEL = 2'b00; +parameter LNDIV_RATIO = 4'b0000; +parameter LNDIV_EN = 1'b0; +parameter D0LN_TX_REASGN_A = 2'b00; +parameter D0LN_TX_REASGN_B = 2'b01; +parameter D0LN_TX_REASGN_C = 2'b10; +parameter D0LN_RX_HS_21BIT_MODE = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D0LN_RX_W_LENDIAN = 1'b1; +parameter D0LN_RX_REASGN_A = 2'b00; +parameter D0LN_RX_REASGN_B = 2'b01; +parameter D0LN_RX_REASGN_C = 2'b10; +parameter HSRX_LNSEL = 3'b111; +parameter EQ_RS_LN0 = 3'b001; +parameter EQ_CS_LN0 = 3'b101; +parameter PGA_GAIN_LN0 = 4'b0110; +parameter PGA_BIAS_LN0 = 4'b1000; +parameter EQ_PBIAS_LN0 = 4'b0100; +parameter EQ_ZLD_LN0 = 4'b1000; +parameter D1LN_TX_REASGN_A = 2'b00; +parameter D1LN_TX_REASGN_B = 2'b01; +parameter D1LN_TX_REASGN_C = 2'b10; +parameter D1LN_RX_HS_21BIT_MODE = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D1LN_RX_W_LENDIAN = 1'b1; +parameter D1LN_RX_REASGN_A = 2'b00; +parameter D1LN_RX_REASGN_B = 2'b01; +parameter D1LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN1 = 3'b001; +parameter EQ_CS_LN1 = 3'b101; +parameter PGA_GAIN_LN1 = 4'b0110; +parameter PGA_BIAS_LN1 = 4'b1000; +parameter EQ_PBIAS_LN1 = 4'b0100; +parameter EQ_ZLD_LN1 = 4'b1000; +parameter D2LN_TX_REASGN_A = 2'b00; +parameter D2LN_TX_REASGN_B = 2'b01; +parameter D2LN_TX_REASGN_C = 2'b10; +parameter D2LN_RX_HS_21BIT_MODE = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D2LN_RX_W_LENDIAN = 1'b1; +parameter D2LN_RX_REASGN_A = 2'b00; +parameter D2LN_RX_REASGN_B = 2'b01; +parameter D2LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN2 = 3'b001; +parameter EQ_CS_LN2 = 3'b101; +parameter PGA_GAIN_LN2 = 4'b0110; +parameter PGA_BIAS_LN2 = 4'b1000; +parameter EQ_PBIAS_LN2 = 4'b0100; +parameter EQ_ZLD_LN2 = 4'b1000; +endmodule + module GTR12_QUAD (...); endmodule @@ -1926,6 +2464,18 @@ endmodule module GTR12_PMAC (...); endmodule +module GTR12_QUADA (...); +endmodule + +module GTR12_UPARA (...); +endmodule + +module GTR12_PMACA (...); +endmodule + +module GTR12_QUADB (...); +endmodule + module DQS (...); input DQSIN,PCLK,FCLK,RESET; input [3:0] READ; @@ -1941,4 +2491,3 @@ parameter RD_PNTR = 3'b000; parameter DQS_MODE = "X1"; parameter HWL = "false"; endmodule - From eed3bc243f1e17812604eacafbc02b111f64ceb3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 2 Jul 2025 11:54:19 +0200 Subject: [PATCH 27/30] verific: enable replacing const exprs in static elaboration by default --- frontends/verific/verific.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d12f8a5a5..d83db3410 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3465,11 +3465,13 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); + RuntimeFlags::SetVar("veri_replace_const_exprs", 1); #endif #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); + RuntimeFlags::SetVar("vhdl_replace_const_exprs", 1); RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); From 99f7d79abb6a4514c141366237f510b1c1ec6679 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 5 Jul 2025 00:23:55 +0000 Subject: [PATCH 28/30] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3c2bc11b6..26bc60be3 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+29 +YOSYS_VER := 0.54+37 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 60f126cd00c94892782470192d6c9f7abebe7c05 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 7 Jul 2025 11:16:07 +0200 Subject: [PATCH 29/30] Release version 0.55 --- CHANGELOG | 6 +++++- Makefile | 4 ++-- docs/source/conf.py | 2 +- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 537c5682d..b6b7c587b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,12 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.54 .. Yosys 0.55-dev +Yosys 0.54 .. Yosys 0.55 -------------------------- + * Various + - read_verilog: Implemented SystemVerilog unique/priority if. + - "attrmap" pass is able to alter memory attributes. + - verific: Support SVA followed-by operator in cover mode. Yosys 0.53 .. Yosys 0.54 -------------------------- diff --git a/Makefile b/Makefile index 26bc60be3..074553918 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.54+37 +YOSYS_VER := 0.55 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -183,7 +183,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index 100605336..05dcb7d5f 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2025 YosysHQ GmbH' -yosys_ver = "0.54" +yosys_ver = "0.55" # select HTML theme html_theme = 'furo-ys' From 8af60b7e17d2cf1d092b06ca180868146ca3dd03 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 7 Jul 2025 12:40:53 +0200 Subject: [PATCH 30/30] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index b6b7c587b..d8f2f8804 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.55 .. Yosys 0.56-dev +-------------------------- + Yosys 0.54 .. Yosys 0.55 -------------------------- * Various diff --git a/Makefile b/Makefile index 074553918..b7928f33a 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.55 +YOSYS_VER := 0.55+0 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -183,7 +183,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 60f126c.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)